Martin Ana M Keim

US Patent:

7512508, Mar 31, 2009

Filed:

Sep 6, 2005

Appl. No.:

11/221395

Inventors:

Janusz Rajski - West Linn OR, US
Gang Chen - Wilsonville OR, US
Martin Keim - Sherwood OR, US
Nagesh Tamarapalli - Wilsonville OR, US
Manish Sharma - Wilsonville OR, US
Huaxing Tang - Wilsonville OR, US

International Classification:

G01R 31/26
G06F 11/22

US Classification:

702118, 702181, 702 81, 438 14

Abstract:

Methods, apparatus, and systems for computing and analyzing integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.

US Patent:

7987442, Jul 26, 2011

Filed:

Sep 6, 2005

Appl. No.:

11/221394

Inventors:

Janusz Rajski - West Linn OR, US
Gang Chen - Wilsonville OR, US
Martin Keim - Sherwood OR, US
Nagesh Tamarapalli - Wilsonville OR, US
Manish Sharma - Wilsonville OR, US
Huaxing Tang - Wilsonville OR, US

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 17/50
G06F 9/455
G06F 11/00

US Classification:

716136, 716106, 714737

Abstract:

Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from corresponding observation point combinations. In this exemplary method, the observation point combinations indicate the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern. Further, the one or more fault dictionaries in one embodiment are generated by: (a) for a first defect candidate, storing one or more first indicators indicative of test patterns detecting the first defect candidate, and (b) for a second defect candidate, storing at least a second indicator indicative of the test patterns that detect the second defect candidate, the second indicator comprising a bit mask that indicates which of the test patterns detecting the first defect candidate also detect the second defect candidate.

US Patent:

20060053357, Mar 9, 2006

Filed:

Sep 6, 2005

Appl. No.:

11/221373

Inventors:

Janusz Rajski - West Linn OR, US
Gang Chen - Wilsonville OR, US
Martin Keim - Sherwood OR, US
Nagesh Tamarapalli - Willsonville OR, US
Manish Sharma - Wilsonville OR, US
Huaxing Tang - Wilsonville OR, US

International Classification:

G01R 31/28
G06F 11/00

US Classification:

714742000

Abstract:

Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, design defect extraction rules are derived at least partially from a set of design manufacturing rules. Potential defects are extracted from a representation of an integrated circuit layout using the design defect extraction rules. Circuit test stimuli applied during one or more circuit tests are determined. Test responses resulting from the applied circuit tests are evaluated to identify integrated circuits that fail and to identify the occurrence in the failing integrated circuits of one or more potential types of defects associated with the applied circuit tests. Information concerning the repetitive identification in the failing integrated circuits of the occurrence of potential types of defects is collected and analyzed to determine the likelihood of potential types of defects being present in integrated circuits manufactured in accordance with the layout.

US Patent:

20090210183, Aug 20, 2009

Filed:

Mar 31, 2009

Appl. No.:

12/415806

Inventors:

Janusz Rajski - West Linn OR, US
Gang Chen - Wilsonville OR, US
Martin Keim - Sherwood OR, US
Nagesh Tamarapalli - Wilsonville OR, US
Manish Sharma - Wilsonville OR, US
Huaxing Tang - Wilsonville OR, US

International Classification:

G06F 19/00

US Classification:

702 84, 702118

Abstract:

Methods, apparatus, and systems for computing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein, information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.

US Patent:

20230049928, Feb 16, 2023

Filed:

Aug 28, 2020

Appl. No.:

17/757013

Inventors:

- Plano TX, US
Martin Keim - Sherwood OR, US

International Classification:

G11C 29/44
G06F 3/06

Abstract:

A memory device can sense stored data during memory read operations using a reference trim, and a memory built-in self-test system can perform a multiple step process to set the reference trim for the memory device. The memory built-in self-test system can set a reference trim range that corresponds to a range of available reference trim values and then select one of the reference trim values in the reference trim range as the reference trim for the memory device. The memory built-in self-test system can set the reference trim range by prompting performance of the memory read operations using different positions of the reference trim range relative to read characteristics of the memory device and set a position for the reference trim range relative to the read characteristics of the memory device based on failures of the memory device to correctly sense the stored data during the memory read operations.

US Patent:

20180335475, Nov 22, 2018

Filed:

May 21, 2018

Appl. No.:

15/985679

Inventors:

- Wilsonville OR, US
Martin Keim - Sherwood OR, US

International Classification:

G01R 31/3177
G01R 31/317

Abstract:

A reconfigurable scan network in a circuit is configured such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault. A test pattern having a length equal to a length of the second path is shifted into the reconfigurable scan network, and a part or a whole of the test pattern is then shifted out from the reconfigurable scan network. The part or the whole of the test pattern being shifted out is analyzed to determine whether the programmable component has the stuck-at fault.