Mark C Hakey

US Patent:

6338934, Jan 15, 2002

Filed:

Aug 26, 1999

Appl. No.:

09/383452

Inventors:

Kuang-Jung R. Chen - Poughkeepsie NY
Mark C. Hakey - Milton VT
Steven J. Holmes - Milton VT
Paul A. Rabidoux - Winooski VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03F 7004

US Classification:

4302701, 430914, 430919

Abstract:

A photo resist composition contains a polymer resin, a first photo acid generator (PAG) requiring a first dose of actinic energy to generate a first photo acid, and a photo base generator (PBG) requiring a second dose of actinic energy, different from the first dose, to generate a photo base. The amounts and types of components in the photo resist are selected to produce a hybrid resist image. Either the first photo acid or photo base acts as a catalyst for a chemical transformation in the resist to induce a solubility change. The other compound is formulated in material type and loading in the resist such that it acts as a quenching agent. The catalyst is formed at low doses to induce the solubility change and the quenching agent is formed at higher doses to counterbalance the presence of the catalyst. Accordingly, the same frequency doubling effect of conventional hybrid resist compositions may be obtained, however, either a line or a space may be formed at the edge of an aerial image. Feature size may also be influenced by incorporating a quenching agent into the resist composition that does not require photo generation.

US Patent:

6342323, Jan 29, 2002

Filed:

Mar 13, 2000

Appl. No.:

09/523796

Inventors:

William Hsioh-Lien Ma - Fishkill NY
David Vaclay Horak - Essex Junction VT
Toshiharu Furukawa - Essex Junction VT
Steven J. Holmes - Milton VT
Mark Charles Hakey - Milton VT

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G03F 900

US Classification:

430 22, 356399

Abstract:

An improved alignment methodology for lithography. In the method, a third level is aligned to two previous levels, where the alignment mark location for the third level is calculated based upon the two previous levels in both the x- and y-directions. A preferred embodiment of the invention relates to a lithography alignment method for aligning a third level of a semiconductor device relative to first and second previous levels of the device. The method comprises the steps of forming first and second patterns at the first and second levels respectively, and determining offsets of the first and second patterns in two orthoginal directions. An optimum location for a third pattern in the third level is then determined based on an average of the offsets of the first and second patterns.

US Patent:

6344416, Feb 5, 2002

Filed:

Mar 10, 2000

Appl. No.:

09/523480

Inventors:

Toshiharu Furukawa - Essex Junction VT
Mark C. Hakey - Fairfax VT
Steven J. Holmes - Milton VT
David V. Horak - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21311

US Classification:

438694, 438 4, 438759, 438911

Abstract:

Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production runs. The present invention radially varies the thickness and/or composition of a semiconductor film to compensate for a known radial variation in the semiconductor film that is caused by performing a subsequent semiconductor processing step on the semiconductor film. Additionally, methods and apparatuses are disclosed that can introduce deliberate semiconductor film variations to determine optimal device characteristics or produce small production runs. Introducing semiconductor film variations, such as thickness variations and/or composition variations, allow different devices to be made. A number of devices may be made having variations in semiconductor film.

US Patent:

6358813, Mar 19, 2002

Filed:

Nov 15, 2000

Appl. No.:

09/713766

Inventors:

Steven J. Holmes - Milton VT
Charles Black - White Plains NY
David J. Frank - Yorktown Heights NY
Toshiharu Furukawa - Essex Junction VT
Mark C. Hakey - Franklin VT
David V. Horak - Essex Junction VT
William Hsioh-Lien Ma - Fishkill NY
Keith R. Milkove - Beacon NY
Kathryn W. Guarini - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2120

US Classification:

438398, 438397, 438396, 438739

Abstract:

Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

US Patent:

6372412, Apr 16, 2002

Filed:

Feb 10, 1998

Appl. No.:

09/021924

Inventors:

Mark C. Hakey - Milton VT
Steven J. Holmes - Milton VT
David V. Horak - Essex Junction VT
Ahmad D. Katnani - Poughkeepsie NY
Niranjan M. Patel - Wappingers Falls NY
Paul A. Rabidoux - Winooski VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03F 730

US Classification:

430325, 430326, 430328, 430330

Abstract:

A photoresist composition is disclosed having both negative tone and positive tone responses, giving rise to spaces being formed in the areas of diffraction which are exposed to intermediate amounts of radiation energy. This resist material may be used to print doughnut shapes or may be subjected to a second masking step, to print lines. Additionally, larger and smaller features may be obtained using a gray-scale filter in the reticle, to create larger areas of intermediate exposure areas.

US Patent:

6376873, Apr 23, 2002

Filed:

Apr 7, 1999

Appl. No.:

09/287410

Inventors:

Toshiharu Furukawa - Essex Junction VT
Mark C. Hakey - Milton VT
Steven J. Holmes - Milton VT
David V. Horak - Essex Junction VT
Thomas S. Kanarsky - Hopewell Junction NY
Jeffrey J. Welser - Stamford CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27108

US Classification:

257301, 257302, 257303, 257304, 257305

Abstract:

A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness. A signal transfer device includes a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap, a gate insulator having a gate insulator thickness formed on the trench side wall above the first buried strap, wherein the gate insulator thickness is less than the trench-top dielectric thickness, and a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator.

US Patent:

6387783, May 14, 2002

Filed:

Apr 26, 1999

Appl. No.:

09/299267

Inventors:

Toshiharu Furukawa - Essex Junction VT
Mark C. Hakey - Fairfax VT
Steven J. Holmes - Milton VT
David V. Horak - Essex Junction VT
Paul A. Rabidoux - Winooski VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2128

US Classification:

438574, 438182, 438300, 438579

Abstract:

Methods for forming a T-gate on a substrate are provided that employ a hybrid resist. The hybrid resist specifically is employed to define a base of the T-gate on the substrate with very high resolution. To define a base of the T-gate, a hybrid resist layer is deposited on the substrate. A mask having a reticle feature with an edge is provided and is positioned above the hybrid resist layer so that the edge of the reticle feature is above a desired location for the base of the T-gate. Thereafter, the hybrid resist layer is exposed to radiation through the mask, and the exposed hybrid resist layer is developed to define an opening therein for the base of the T-gate. Preferably the loop feature formed in the hybrid resist layer by the reticle feature during exposure is trimmed. The T-gate may be completed by employing any known T-gate fabrication techniques.

US Patent:

6391426, May 21, 2002

Filed:

Jun 19, 1997

Appl. No.:

08/878136

Inventors:

Mark C. Hakey - Milton VT
Steven J. Holmes - Milton VT
David V. Horak - Essex Junction VT
William H. Ma - Fishkill NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B32B 100

US Classification:

428174, 428141, 430 11, 430 14

Abstract:

A high capacitance storage node structure is created in a substrate by patterning a hybrid resist ( ) to produce both negative tone ( ) and positive tone ( ) areas in the exposed region ( ). After removal of the positive tone areas ( ), the substrate ( ) is etched using the unexposed hybrid resist ( ) and negative tone area ( ) as a mask. This produces a trench ( ) in the substrate ( ) with a centrally located, upwardly projecting protrusion ( ). The capacitor ( ) is then created by coating the sidewalls of the trench ( ) and protrusion ( ) with dielectric ( ) and filling the trench with conductive material ( ) such as polysilicon.