Margaret R Charlebois

US Patent:

8015526, Sep 6, 2011

Filed:

Jun 13, 2008

Appl. No.:

12/138871

Inventors:

Margaret R. Charlebois - Jericho VT, US
David J. Hathaway - Underhill VT, US
Jason E. Rotella - Mineville NY, US
Douglas W. Stout - Milton VT, US
Ivan L. Wemple - Shelburne VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716108, 716109

Abstract:

A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

US Patent:

8464199, Jun 11, 2013

Filed:

May 16, 2012

Appl. No.:

13/472814

Inventors:

Margaret R. Charlebois - Jericho VT, US
Christopher D. Hanudel - Essex Junction VT, US
Robert D. Herzl - South Burlington VT, US
David W. Milton - Underhill VT, US
Clarence R. Ogilvie - Huntington VT, US
Paul M. Schanely - Essex Junction VT, US
Tad J. Wilder - South Hero VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716132, 716113, 716134

Abstract:

A method for designing an integrated circuit. A computer determines, for one or more paths in a circuit design, for a value of a design variable at which timing closure of the circuit design is achieved, an approximate slope of a function representing path delay as a function of the design variable. When the computer determines that one of the approximate slopes is not within a defined slope range, the computer determines an adjustment direction and an adjustment value based in part on the magnitude by which the slope is not within the defined slope range. The computer changes the circuit design of the path associated with the out-of-range slope, based in part on the adjustment direction and the adjustment value, so as to bring the slope within the defined slope range.

US Patent:

20070226667, Sep 27, 2007

Filed:

Mar 24, 2006

Appl. No.:

11/277385

Inventors:

Thomas Chadwick - Essex Junction VT, US
Margaret Charlebois - Jericho VT, US
David Hathaway - Underhill VT, US
Jason Rotella - Mineville NY, US
Douglas Stout - Milton VT, US
Ivan Wemple - Shelburne VT, US

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716006000

Abstract:

A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

US Patent:

20130041608, Feb 14, 2013

Filed:

Aug 8, 2011

Appl. No.:

13/204812

Inventors:

Margaret R. Charlebois - Jericho VT, US
Rashmi D. Chatty - Oviedo FL, US
Christopher D. Hanudel - Essex Junction VT, US
Robert D. Herzl - South Burlington VT, US
David W. Milton - Underhill VT, US
Clarence R. Ogilvie - Huntington VT, US
Matthew P. Szafir - Williston VT, US
Tad J. Wilder - South Hero VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 19/00

US Classification:

702 79

Abstract:

Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.

US Patent:

20140028365, Jan 30, 2014

Filed:

Jul 26, 2012

Appl. No.:

13/558498

Inventors:

Margaret R. Charlebois - Jericho VT, US
Rashmi D. Chatty - Williston VT, US
Christopher D. Hanudel - Essex Junction VT, US
Robert D. Herzl - South Burlington VT, US
David W. Milton - Underhill VT, US
Clarence R. Ogilvie - Huntington VT, US
Paul M. Schanely - Essex Junction VT, US
Matthew P. Szafir - Williston VT, US
Tad J. Wilder - South Hero VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H03H 11/26

US Classification:

327276

Abstract:

Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.