Lyle V Rennick

US Patent:

6522204, Feb 18, 2003

Filed:

Nov 28, 2000

Appl. No.:

09/723574

Inventors:

Lyle V. Rennick - Cupertino CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03L 706

US Classification:

331 1A, 331 17, 331 25, 327157, 327159, 375376, 375374

Abstract:

A phase-locked loop (PLL), particularly useful for ADSL frequency locking applications, uses inexpensive external components in combination with versatile logic that can be implemented in a programmable logic device or an application specific integrated circuit. The PLL has the ability to revert to center-frequency operation in the absence of a timing reference and to adapt to a variety of reference frequencies through logic selection.

US Patent:

42323819, Nov 4, 1980

Filed:

Jun 8, 1979

Appl. No.:

6/047377

Inventors:

Lyle V. Rennick - Mission Viejo CA
Julian W. Macias - Irvine CA

Assignee:

Northrop Corporation - Hawthorne CA

International Classification:

H04B 106

US Classification:

367135

Abstract:

A noise-cancellation scheme in a system receiving acoustic information signals, where the system is carried in a vehicle having self-generated engine noise. An engine rotation sensor generates pulses driving a synchronous type filter device which passes only the engine noise frequency and its harmonics. The latter signal is then subtracted from the total input signal having information and noise combined. One filter circuit comprises a phase-locked loop with a multiplying counter whose output goes to a multiplexer having a plurality of grounded capacitors connected thereto.

US Patent:

42887828, Sep 8, 1981

Filed:

Aug 24, 1979

Appl. No.:

6/069258

Inventors:

Ronald S. Bader - Cupertino CA
Lyle V. Rennick - Cupertino CA
Robert H. Wallis - Portola Valley CA

Assignee:

Compression Labs, Inc. - Cupertino CA

International Classification:

G06K 968

US Classification:

3401463Q

Abstract:

A high speed character matcher and method for measuring the similarity between a pair of binary patterns representing two-dimensional images. The patterns are compared on a bit by bit basis and when a discrepancy is detected, it is assigned an error penalty which is based on the two-dimensional context in which the error occurred. The types of error context which are typical in the comparison of distorted but otherwise similar characters are given a lower error than those typically encountered in the comparison of dissimilar characters.

US Patent:

44109164, Oct 18, 1983

Filed:

Jul 9, 1981

Appl. No.:

6/281721

Inventors:

William K. Pratt - San Jose CA
Ronald S. Bader - Cupertino CA
Wen-Hsiung Chen - Sunnyvale CA
Lyle V. Rennick - Cupertino CA
Robert H. Wallis - Portola Valley CA

Assignee:

Compression Labs, Inc. - Cupertino CA

International Classification:

H04N 140

US Classification:

358263

Abstract:

A dual mode facsimile data compression technique which possesses the advantage of symbol recognition and extended run-length coding methods. In operation, a symbol blocking operator isolates digital raster data representing valid alphanumeric characters and document symbols. The first symbol encoungered is placed in a memory or library and as each new symbol is detected, it is compared with each entry of the library. If the comparison is within a predetermined tolerance, a library identification code representing the symbol is generated and transmitted along with the symbol location coordinates. Otherwise, the new symbol is placed in the library and its digital pattern and location is transmitted. A scoring system determines which elements of the library are to be replaced by new prototypes once the library is filled. Non-isolated symbols are coded by a two-dimensional run-length coding method for transmission.