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Lee D Mcfearin

age ~58

from Plano, TX

Also known as:
  • Lee Dobson Mcfearin
  • Lee Mc Fearin
  • Lee D Mcfearn
  • Mcfearin Lee
Phone and address:
7508 Benelux Ct, Plano, TX 75025
972-517-6928

Lee Mcfearin Phones & Addresses

  • 7508 Benelux Ct, Plano, TX 75025 • 972-517-6928
  • Dallas, TX

Us Patents

  • Container Based Crossconnect

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  • US Patent:
    7251416, Jul 31, 2007
  • Filed:
    May 8, 2003
  • Appl. No.:
    10/431795
  • Inventors:
    Lakshman S. Tamil - Plano TX, US
    Glen Collier - Plano TX, US
    Mitch Entezari - Highland Village TX, US
    Allesandro Fabbri - Richardson TX, US
    Gopalakrishnan Hari - Plano TX, US
    Justin Hunt - Wylie TX, US
    Quan Jiang - Plano TX, US
    Bing Li - San Diego CA, US
    Lee McFearin - Plano TX, US
    Joseph M. McQuade - Gilbert AZ, US
    Earl Ponceti - McKinney TX, US
    Scott A. Rothrock - Ashburn VA, US
    Frederick A. Rush - Austin TX, US
    Alexander A. Smith - Cupertino CA, US
    David Wolf - Allen TX, US
  • Assignee:
    Yotta networks, LLC - Greenbrac CA
  • International Classification:
    H04J 14/00
  • US Classification:
    398 47, 398 45, 398 48, 398 50, 398 51, 398 54, 370351, 370352, 370355, 370389
  • Abstract:
    Systems and methods for optical cross connects which switch data at a container (packet) level. In one embodiment, a plurality of optical switch edges are coupled to an optical switch core via a minimal number of optical fibers. The switch core is configured to optically switch data from an ingress edge to one of a plurality of egress edges in a nonblocking fashion. The ingress edge receives data streams and distributes the data among a plurality of container processors. Each of these container processors produces an optical signal of a different wavelength, which can then be multiplexed with others to form a multiple-wavelength optical signal that is transmitted to the switch core. The switch core then switches successive portions (containers) of the multiple-wavelength signal to the egress edges to which they are respectively destined. The respective egress edges perform the reverse of this process to form output data signals.
  • Higher Radix Multiplier With Simplified Partial Product Generator

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  • US Patent:
    20030018678, Jan 23, 2003
  • Filed:
    Feb 25, 2002
  • Appl. No.:
    10/080707
  • Inventors:
    David Matula - Dallas TX, US
    Peter-Michael Seidel - Dallas TX, US
    Lee McFearin - Plano TX, US
  • International Classification:
    G06F007/52
  • US Classification:
    708/620000, 708/628000
  • Abstract:
    A method and apparatus for improving the efficiency of hardware-based binary multiplication. By using radix-32 and radix-256 multipliers where each radix-32 digit is represented by two radix-7 digits and each radix-256 digit is represented by three radix-11 digits, the digit magnitudes are in power of two, which simplifies the implementation of the partial product generation. The partial products depending on multiples of the radices 7 or 11 can be separately accumulated, with multiplication by the radix a pre- or post-computation option.
  • System And Method For Shared Memory Ownership Using Context

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  • US Patent:
    20200050376, Feb 13, 2020
  • Filed:
    Oct 21, 2019
  • Appl. No.:
    16/658899
  • Inventors:
    - Plano TX, US
    Lee Dobson McFearin - Plano TX, US
    Alan Gatherer - Richardson TX, US
    Hao Luan - Plano TX, US
  • International Classification:
    G06F 3/06
    G06F 12/084
    G06F 12/0888
    G06F 12/14
    G06F 9/50
  • Abstract:
    It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.
  • Processing Units Having Triangular Load Protocol

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  • US Patent:
    20180321939, Nov 8, 2018
  • Filed:
    May 4, 2017
  • Appl. No.:
    15/586937
  • Inventors:
    - Plano TX, US
    Sushma Wokhlu - Frisco TX, US
    Peter Yan - Frisco TX, US
    Ashish Rai Shrivastava - Plano TX, US
    Tong Sun - Allen TX, US
    Lee Dobson McFearin - Plano TX, US
  • Assignee:
    Futurewei Technologies, Inc. - Plano TX
  • International Classification:
    G06F 9/30
    G06F 3/06
    G06F 9/38
  • Abstract:
    Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.
  • System And Method For Shared Memory Ownership Using Context

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  • US Patent:
    20170371570, Dec 28, 2017
  • Filed:
    Jun 24, 2016
  • Appl. No.:
    15/192453
  • Inventors:
    - Plano TX, US
    Lee Dobson Mcfearin - Plano TX, US
    Alan Gatherer - Richardson TX, US
    Hao Luan - Plano TX, US
  • International Classification:
    G06F 3/06
    G06F 12/084
    G06F 12/0815
  • Abstract:
    It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.
  • Scalable Autonomic Message-Transport With Synchronization

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  • US Patent:
    20170293512, Oct 12, 2017
  • Filed:
    Apr 12, 2016
  • Appl. No.:
    15/096966
  • Inventors:
    - Plano TX, US
    Alan Gatherer - Richardson TX, US
    Alex Elisa Chandra - Plano TX, US
    Lee Dobson Mcfearin - Plano TX, US
    Mark Brown - Little Elm TX, US
    Debashis Bhattacharya - Plano TX, US
    Fang Yu - San Jose CA, US
    Xingfeng Chen - Shanghai, CN
    Yan Bei - Shanghai, CN
    Ke Ning - Shenzhen, CN
    Chushun Huang - Shenzhen, CN
    Tong Sun - Allen TX, US
    Xiaotao Chen - Basking Ridge NJ, US
  • International Classification:
    G06F 9/54
    G06F 13/28
  • Abstract:
    Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.
  • Noc Interconnect With Linearly-Tunable Qos Guarantees For Real-Time Isolation

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  • US Patent:
    20170293586, Oct 12, 2017
  • Filed:
    Apr 12, 2016
  • Appl. No.:
    15/097091
  • Inventors:
    - Plano TX, US
    Alex Elisa Chandra - Plano TX, US
    Lee Dobson McFearin - Plano TX, US
    Fang Yu - San Jose CA, US
    Alan Gatherer - Richardson TX, US
  • International Classification:
    G06F 13/42
    G06F 13/20
    G06F 15/78
  • Abstract:
    Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m−k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.
  • Space And Time Aware Organization And Isolation Of Components In Real Time Systems

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  • US Patent:
    20170168792, Jun 15, 2017
  • Filed:
    Dec 14, 2016
  • Appl. No.:
    15/378714
  • Inventors:
    - Plano TX, US
    Alan Gatherer - Richardson TX, US
    Mark Brown - Little Elm TX, US
    Lee Dobson McFearin - Plano TX, US
    Alex Elisa Chandra - Plano TX, US
    Ashish Rai Shrivastava - Plano TX, US
  • International Classification:
    G06F 9/45
  • Abstract:
    A method includes obtaining, by a first processor, a first software architecture description file and obtaining, by the first processor, a platform independent model file. The method also includes obtaining, by the first processor, a platform architecture definition file and performing, by the first processor, a first source-to-source compilation in accordance with the first software architecture description file, the platform independent model file, and the platform architecture definition file, to produce generated interface code. Additionally, the method includes generating, by the first processor, run time code, in accordance with the generated interface code and running, by a second processor in real time, the run time code.

Resumes

Lee Mcfearin Photo 1

Senior Principal Software Engineer

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Location:
Dallas, TX
Industry:
Telecommunications
Work:
Raytheon
Senior Principal Software Engineer

Futurewei Technologies
Senior Staff Software Engineer

Crane Aerospace & Electronics Dec 2002 - Dec 2009
Software Lead and Manager and Principal Architect

Southern Methodist University Dec 2002 - Dec 2009
Adjunct Faculty

Yotta Networks 2000 - 2002
Software Lead
Education:
Southern Methodist University 1996 - 2002
Doctorates, Doctor of Philosophy, Computer Engineering
Southern Methodist University 1993 - 1996
Southern Methodist University 1985 - 1989
Skills:
Software Engineering
Algorithms
C++
C
Embedded Systems
System Architecture
Perl
Digital Signal Processors
Embedded Software
Software Design
Object Oriented Design
Software Development
Lee Mcfearin Photo 2

Lee Mcfearin

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Vehicle Records

  • Lee Mcfearin

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  • Address:
    7508 Benelux Ct, Plano, TX 75025
  • Phone:
    972-517-6928
  • VIN:
    5FNRL38857B008245
  • Make:
    HONDA
  • Model:
    ODYSSEY
  • Year:
    2007

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Lee McFearin Plano TX

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