Lance C Cheney

US Patent:

7793187, Sep 7, 2010

Filed:

Jun 7, 2007

Appl. No.:

11/759832

Inventors:

Allan Wong - Folsom CA, US
Lance Cheney - Davis CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 31/28
G06F 11/00
G06F 15/00
G06T 1/00
G06F 15/80
G06T 1/20

US Classification:

714736, 714734, 345501, 345505, 345506

Abstract:

Provided are a method and system checking output from multiple execution units. Execution units concurrently execute test instructions to generate test output, wherein test instructions are transferred to the execution units from a cache coupled to the execution units over a bus. The test output from the execution units is compared to determine whether the output from the execution units indicates the execution units are properly concurrently executing test instructions. The result of the comparing of the test output are forwarded to a design test unit.

US Patent:

7904701, Mar 8, 2011

Filed:

Jun 7, 2007

Appl. No.:

11/759840

Inventors:

Anthony Babella - Salida CA, US
Allan Wong - Folsom CA, US
Lance Cheney - Davis CA, US
Brian D. Rauchfuss - Shingle Springs CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/00
G06F 11/00

US Classification:

712227, 714 30

Abstract:

Provided are a method and system for activating a design test mode in a graphics card having multiple execution units. A design test mode is activated in a graphics module comprising multiple execution units coupled to a cache on a bus. The bus is configured to return test instructions from the cache to the execution units in response to a request from one execution unit for the test instructions from the cache in the design test mode. The execution units execute the test instructions during the design test mode. Interrupts are prevented during the design test mode.

US Patent:

20220188967, Jun 16, 2022

Filed:

Mar 2, 2022

Appl. No.:

17/685117

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Josh Mastronarde - Sacramento CA, US
Naveen Matam - Rancho Cordova CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets, With such an interchangeable design, cache or DRAM memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

US Patent:

20220180468, Jun 9, 2022

Filed:

Feb 17, 2022

Appl. No.:

17/674781

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Altug Koker - El Dorado Hills CA, US
Josh Mastronarde - Sacramento CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

US Patent:

20210256654, Aug 19, 2021

Filed:

Jan 29, 2021

Appl. No.:

17/161941

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Josh Mastronarde - Sacramento CA, US
Naveen Matam - Rancho Cordova CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

US Patent:

20210133913, May 6, 2021

Filed:

Oct 13, 2020

Appl. No.:

17/069188

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Altug Koker - El Dorado Hills CA, US
Josh Mastronarde - Sacramento CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

US Patent:

20200294180, Sep 17, 2020

Filed:

Mar 15, 2019

Appl. No.:

16/355303

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Josh Mastronarde - Sacramento CA, US
Naveen Matam - Rancho Cordova CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

US Patent:

20200294181, Sep 17, 2020

Filed:

Mar 15, 2019

Appl. No.:

16/355377

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Altug Koker - El Dorado Hills CA, US
Josh Mastronarde - Sacramento CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.