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Kuan Zhou

age ~49

from Auburndale, MA

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Also known as:
  • Kuan Hu
Related to:
Connected to:

Kuan Zhou Phones & Addresses

  • Auburndale, MA
  • Portland, OR
  • Hillsboro, OR
  • Longmeadow, MA
  • Scarborough, ME
  • Newmarket, NH
  • Riverside, CA
  • Troy, NY
  • Burlington, MA
  • 2098 NW Thorncroft Dr APT 1632, Hillsboro, OR 97124

Skills

Ic • Mixed Signal • Asic • Circuit Design • Cmos • Analog Circuit Design • Semiconductors • Fpga • Verilog • Integrated Circuit Design • Analog • Soc • Vlsi • Cadence Virtuoso • Dft

Industries

Computer Hardware

Us Patents

  • Circuits And Methods Representative Of Spike Timing Dependent Plasticity Of Neurons

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  • US Patent:
    8600919, Dec 3, 2013
  • Filed:
    Aug 25, 2009
  • Appl. No.:
    13/058754
  • Inventors:
    Chi-Sang Poon - Lexington MA, US
    Joshua Jen Choa Monzon - Somerville MA, US
    Kuan Zhou - Scarborough ME, US
  • Assignee:
    Massachusetts Institute of Technology - Cambridge MA
  • International Classification:
    G06N 3/00
  • US Classification:
    706 33
  • Abstract:
    A neuromorphic circuit performs functions representative of spiking timing dependent plasticity of a synapse.

  • Pulse Modulated Neural Integrator Circuit

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  • US Patent:
    8504503, Aug 6, 2013
  • Filed:
    Jul 15, 2010
  • Appl. No.:
    12/837070
  • Inventors:
    Chi-Sang Poon - Lexington MA, US
    Joshua Jen Monzon - Somerville MA, US
    Guy Rachmuth - Charlotte NC, US
    Kuan Zhou - Scarborough ME, US
  • Assignee:
    Massachusetts Institute of Technology - Cambridge MA
  • International Classification:
    G06F 15/18
    G06J 1/00
    G06N 3/00
  • US Classification:
    706 33
  • Abstract:
    A pulse modulated neural integrator circuit is comprised of discrete analog electronic components and has a plurality of discrete stable states. In some embodiments, the pulse modulated neural integrator circuit is fabricated in whole or in part on an integrated circuit substrate using analog VLSI techniques. A phase locked loop circuit can use the pulse modulated neural integrator circuit in place of some conventional phase locked loop circuits.

  • Duty Cycle Correction System And Low Dropout (Ldo) Regulator Based Delay-Locked Loop (Dll)

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  • US Patent:
    20210320652, Oct 14, 2021
  • Filed:
    Jun 24, 2021
  • Appl. No.:
    17/357456
  • Inventors:
    - Santa Clara CA, US
    Roger Cheng - San Jose CA, US
    Hari Venkatramani - San Jose CA, US
    Navneet Dour - El Dorado Hills CA, US
    Mozhgan Mansuri - Hillsboro OR, US
    Bryan Casper - Ridgefield WA, US
    Frank O'Mahony - Portland OR, US
    Ganesh Balamurugan - Hillsboro OR, US
    Kuan Zhou - Portland OR, US
    Sridhar Tirumalai - Chandler AZ, US
    Krishnamurthy Venkataramana - Folsom CA, US
    Alex Thomas - El Dorado Hills CA, US
    Quoc Nguyen - El Dorado Hills CA, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H03K 5/156
    H03L 7/081
    G11C 7/22
    G06F 1/08
    G11C 7/10
  • Abstract:
    An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

  • Duty Cycle Correction System And Low Dropout (Ldo) Regulator Based Delay-Locked Loop (Dll)

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  • US Patent:
    20200106430, Apr 2, 2020
  • Filed:
    Sep 27, 2018
  • Appl. No.:
    16/144949
  • Inventors:
    - Santa Clara CA, US
    Roger Cheng - San Jose CA, US
    Hari Venkatramani - San Jose CA, US
    Navneet Dour - El Dorado Hills CA, US
    Mozhgan Mansuri - Hillsboro OR, US
    Bryan Casper - Ridgefield WA, US
    Frank O'Mahony - Portland OR, US
    Ganesh Balamurugan - Hillsboro OR, US
    Kuan Zhou - Portland OR, US
    Sridhar Tirumalai - Chandler AZ, US
    Krishnamurthy Venkataramana - Folsom CA, US
    Alex Thomas - El Dorado Hills CA, US
    Quoc Nguyen - El Dorado Hills CA, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H03K 5/156
    H03L 7/081
    G11C 7/22
    G11C 7/10
    G06F 1/08
  • Abstract:
    An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Resumes

Kuan Zhou Photo 1

Kuan Zhou

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Location:
91 Central St, Auburndale, MA 02466
Industry:
Computer Hardware
Skills:
Ic
Mixed Signal
Asic
Circuit Design
Cmos
Analog Circuit Design
Semiconductors
Fpga
Verilog
Integrated Circuit Design
Analog
Soc
Vlsi
Cadence Virtuoso
Dft
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