Kenneth C Debacker

US Patent:

52952584, Mar 15, 1994

Filed:

Jan 5, 1990

Appl. No.:

7/461250

Inventors:

Douglas E. Jewett - Austin TX
Tom Bereiter - Austin TX
Brian Vetter - Austin TX
Randall G. Banton - Austin TX
Richard W. Cutts - Georgetown TX
Donald C. Westbrook - late of Austin TX
Kyran W. Fey - Pfluggerville TX
John Pozdro - Austin TX
Kenneth C. Debacker - Austin TX
Nikhil A. Mehta - Austin TX

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1118
G06F 1120
G06F 1216

US Classification:

395575

Abstract:

A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.

US Patent:

51931753, Mar 9, 1993

Filed:

Mar 6, 1991

Appl. No.:

7/666495

Inventors:

Richard W. Cutts - Georgetown TX
Peter C. Norwood - Austin TX
Kenneth C. DeBacker - Austin TX
Nikhil A. Mehta - Austin TX
Douglas E. Jewett - Austin TX
John D. Allison - Austin TX
Robert W. Horst - Champaign IL

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1116
G06F 1118
G06F 1128

US Classification:

395575

Abstract:

A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.

US Patent:

60732512, Jun 6, 2000

Filed:

Jun 9, 1997

Appl. No.:

8/871077

Inventors:

Douglas E. Jewett - Austin TX
Tom Bereiter - Austin TX
Bryan Vetter - Austin TX
Randall G. Banton - Austin TX
Richard W. Cutts - Georgetown TX
Donald C. Westbrook - late of Austin TX
Kenneth C. DeBacker - Austin TX
Nikhil A. Mehta - Austin TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1120
G06F 1116

US Classification:

714 7

Abstract:

A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.

US Patent:

62634526, Jul 17, 2001

Filed:

Jan 8, 1999

Appl. No.:

9/226960

Inventors:

Douglas E. Jewett - Austin TX
Tom Bereiter - Austin TX
Bryan Vetter - Austin TX
Randall G. Banton - Austin TX
Richard W. Cutts - Georgetown TX
Donald C. Westbrook - late of Austin TX
Kenneth C. Debacker - Austin TX
Nikhil A. Mehta - Austin TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1118
G06F 1120

US Classification:

714 9

Abstract:

A computer system in a fault-tolerant configuration employees multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.

US Patent:

58900039, Mar 30, 1999

Filed:

Sep 7, 1993

Appl. No.:

8/116950

Inventors:

Richard W. Cutts - Georgetown TX
Kenneth C. Debacker - Austin TX
Robert W. Horst - Champaign IL
Nikhil A. Mehta - Austin TX
Douglas E. Jewett - Austin TX
John David Allison - Austin TX
Richard A. Southworth - Austin TX

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 946

US Classification:

395736

Abstract:

A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.

US Patent:

57581134, May 26, 1998

Filed:

Mar 10, 1997

Appl. No.:

8/815997

Inventors:

Charles E. Peet - Austin TX
John David Allison - Austin TX
Kenneth C. Debacker - Austin TX
Robert W. Horst - Champaign IL

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1200

US Classification:

395379

Abstract:

A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.