Kel D Winters

US Patent:

6466960, Oct 15, 2002

Filed:

May 13, 1999

Appl. No.:

09/311516

Inventors:

Kel D Winters - Fort Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 750

US Classification:

708671, 708704, 3401462

Abstract:

A method and apparatus are provided for performing a fast sum-and-compare operation. The apparatus of the present invention utilizes a single carry save adder in conjunction with a zero detect circuit for performing logic operations to determine whether or not the sum of a plurality of operands is equal to one or more constants. The Carry Save Adder generates a sum, M, and carry, L, that are output from the carry save adder to the zero detect circuit. The zero detect circuit produces internal carry signals that are passed between adjacent bit-cells of the zero detect circuit. The zero detect circuit generates outputs Zk1 through Zkn which are true if the condition A+B+C={k1, k2, k3. . . kn} for all constants k1 through kn. The carry signals propagate through only one bit of the zero detect circuit, thereby providing the sum-and-compare circuit of the present invention with extremely high speed. The constants are programmed into the metal mask of the zero detect circuit, thereby allowing a single circuit design to be used for multiple values of the constant k.

US Patent:

20050015370, Jan 20, 2005

Filed:

Jul 14, 2003

Appl. No.:

10/619225

Inventors:

Donald Stavely - Windsor CO, US
Ted Ziemkowski - Loveland CO, US
Matthew Flach - Fort Collins CO, US
Kel Winters - Fort Collins CO, US

International Classification:

G06F017/30
G06K009/00
G09G005/00
G06F017/00

US Classification:

707006000, 715738000, 707003000, 382181000, 715805000, 715808000, 707104100, 382275000

Abstract:

A system and method is disclosed for delivering information comprising identifying a graphic symbol within an electronic image, communicating the symbol to a database of existing graphic symbols, matching the graphic symbol to one of the existing symbols, and transmitting information associated with the symbol to the electronic image.

US Patent:

6292818, Sep 18, 2001

Filed:

Jan 12, 1999

Appl. No.:

9/228666

Inventors:

Kel D. Winters - Fort Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 702
G06F 750

US Classification:

708671

Abstract:

A sum-and-compare circuit is provided which minimizes propagation delay and which minimizes the amount of die area required to implement the sum-and-compare circuit. The sum-and-compare circuit comprises a propagate/generate logic block followed by a carry-lookahead tree structure. The propagate/generate logic block receives a first operand, A, a second operand, B, and a third operand, J. The first operand A corresponds to an addend, the second operand B corresponds to an augend, and the third operand J corresponds to the twos compliment of the constant K. The propagate/generate logic block comprises logic configured to add the operand A to the operand B to obtain a first sum and logic configured to add the first sum to the operand J to obtain a plurality of propagate signals and a plurality of generate signals, which are then output from the propagate/generate logic block to a carry-lookahead tree structure. The carry-lookahead tree structure comprises logic configured to operate on the propagate and generate signals to produce an output, Gout. The output Gout can be analyzed to determine whether the equation A+B>=K is true.