Keith Michael Jarreau

US Patent:

20100032744, Feb 11, 2010

Filed:

Aug 6, 2009

Appl. No.:

12/537086

Inventors:

Jozef C. Mitros - Richardson TX, US
Keith Jarreau - Plano TX, US
Pinghai Hao - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/788
H01L 21/336

US Classification:

257316, 438257, 257E293, 257E21409

Abstract:

A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.

US Patent:

20110303959, Dec 15, 2011

Filed:

Jun 10, 2010

Appl. No.:

12/797971

Inventors:

Allan T. Mitchell - Heath TX, US
Keith Jarreau - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/788
H01L 21/3205

US Classification:

257315, 438586, 257E293, 257E21295

Abstract:

An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.

US Patent:

20120228724, Sep 13, 2012

Filed:

Mar 11, 2011

Appl. No.:

13/045725

Inventors:

Allan T. Mitchell - Heath TX, US
Mark A. Eskew - Carrollton TX, US
Keith Jarreau - Plano TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H01L 23/525
H01L 21/8239

US Classification:

257410, 438286, 257E23147, 257E21645

Abstract:

In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

US Patent:

20120313180, Dec 13, 2012

Filed:

Aug 8, 2012

Appl. No.:

13/569730

Inventors:

Allan T. Mitchell - Heath TX, US
Mark A. Eskew - Carrollton TX, US
Keith Jarreau - Plano TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H01L 21/8239
H01L 27/088

US Classification:

257368, 438286, 257E2706, 257E21645

Abstract:

In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

US Patent:

20130040449, Feb 14, 2013

Filed:

Oct 16, 2012

Appl. No.:

13/652558

Inventors:

Texas Instruments Incorporated - Dallas TX, US
Keith Jarreau - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/3205

US Classification:

438586, 257E21295

Abstract:

An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.

US Patent:

20170149395, May 25, 2017

Filed:

Jun 3, 2016

Appl. No.:

15/173217

Inventors:

- Dallas TX, US
Andrew Marshall - Dallas TX, US
Harvey J. Stiegler - Plano TX, US
Keith M. Jarreau - Plano TX, US

International Classification:

H03F 3/45
H03F 1/02

Abstract:

An analog differential amplifier circuit, such as an operational transconductance amplifier (OTA), with input offset correction capability. First and second analog floating gate (AFG) devices each include a trim transistor connected in parallel with a series transistor in first and second input legs, respectively, of the amplifier. Floating gate electrodes in the AFG devices are differentially programmed to correct for error in the output signal in response to zero input differential voltage at its inputs. Temperature stability is attained by programming the floating gate electrodes to gate voltages above the floating gate transistors. In one embodiment, the AFG devices each include a second trim transistor sharing the same floating gate electrode; the sum of the currents conducted by the second trim transistors is added, by way of a current mirror, to the tail current applied to the first and second input legs.

US Patent:

20140239409, Aug 28, 2014

Filed:

May 2, 2014

Appl. No.:

14/268493

Inventors:

- Dallas TX, US
Mark A. Eskew - Carrollton TX, US
Keith Jarreau - Plano TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H01L 27/112

US Classification:

257379

Abstract:

In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.