Richard K. Eguchi - Austin TX, US Daniel Hadad - Austin TX, US Chen He - Austin TX, US Katrina M. Prosperi - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C 29/00
US Classification:
714721, 365200, 365201
Abstract:
A method and system are provided for determining an imminent failure of a non-volatile memory array. The method includes: performing a first array integrity read of the memory array until an error is detected; determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage; performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage; and comparing a difference between the first and second threshold voltages to a predetermined value.
Method And Apparatus For Eeprom Emulation For Preventing Data Loss In The Event Of A Flash Block Failure
Chen He - Austin TX, US Richard K. Eguchi - Austin TX, US Daniel Hadad - Austin TX, US Katrina M. Prosperi - Austin TX, US
International Classification:
G06F 12/02
US Classification:
711103, 711E12008
Abstract:
A defect resistant EEPROM emulator () uses one or more redundant and/or spare blocks () in addition to active and alternate blocks () and stores a duplicate copy of EEPROM data records either in the active and redundant blocks or in duplicate rows in the active block to ensure that EEPROM emulation can continue without data loss in the event a catastrophic failure occurs within a block.
Non-Volatile Memory (Nvm) With Imminent Error Prediction
Richard K. Eguchi - Austin TX, US Daniel Hadad - Austin TX, US Chen He - Austin TX, US Katrina M. Prosperi - Austin TX, US
International Classification:
G11C 29/38
US Classification:
714719
Abstract:
A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated.