Kamalesh K Srivastava

US Patent:

6348736, Feb 19, 2002

Filed:

Oct 29, 1999

Appl. No.:

09/429257

Inventors:

Vincent J. McGahay - Poughkeepsie NY
John P. Hummel - Millbrook NY
Joyce Liu - Hopewell Junction NY
Rebecca Mih - Wappingers Falls NY
Kamalesh Srivastava - Wappingers Falls NY
Robert Cook - Minneapolis MN
Stephen E. Greco - LaGrangeville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257774, 257762, 257773

Abstract:

Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

US Patent:

6479884, Nov 12, 2002

Filed:

Jun 29, 2001

Appl. No.:

09/893786

Inventors:

Robert Cook - Minneapolis MN
Stephen E. Greco - LaGrangeville NY
John P. Hummel - Millbrook NY
Joyce Liu - Hopewell Junction NY
Vincent J. McGahay - Poughkeepsie NY
Rebecca Mih - Wappingers Falls NY
Kamalesh Srivastava - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2358

US Classification:

257642, 257643, 257773, 257774, 438623

Abstract:

Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

US Patent:

6531069, Mar 11, 2003

Filed:

Jun 22, 2000

Appl. No.:

09/599761

Inventors:

Kamalesh K. Srivastava - Wappingers Falls NY
Peter C. Wade - Hyde Park NY
William H. Brearley - Poughkeepsie NY
Jonathan H. Griffith - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

C03C 1500

US Classification:

216 67, 216 70, 438 9, 438707, 438710, 20429807, 20429808, 20429811, 20429831, 156345, 118723 R

Abstract:

RIE processing chambers includes arrangements of gas outlets which force gas-flow-shadow elimination. Means are provided to control and adjust the direction of gases to the outlet to modify and control the direction of plasma flow at the wafer surface during processing. Means are provided to either move the exhaust paths for exhaust gases or to open and close exhaust paths sequentially, in a controlled manner, to modify flow directions of ions in the etching plasma. A combination of rotation/oscillation of a magnetic field imposed on the RIE chamber can be employed by rotation of permanent magnetic dipoles about the periphery of the RIE chamber or by controlling current through a coil wrapped around the periphery of the RIE process chamber to enhance the removal of the residues attributable to gas-flow-shadows formed by linear ion paths in the plasma.

US Patent:

6622907, Sep 23, 2003

Filed:

Feb 19, 2002

Appl. No.:

10/078948

Inventors:

Lisa A. Fanti - Hopewell Junction NY
Randolph F. Knarr - Goldens Bridge NY
Erik J. Roggeman - Fishkill NY
Kamalesh K. Srivastava - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B23K 3102

US Classification:

228215, 22818022, 228245, 228256, 438613, 438694, 216 18, 216 41

Abstract:

Start with a semiconductor substrate with contacts exposed through an insulating layer. Form a base over the contacts, with the base composed of at least one metal layer. Then form a conductive metal layer over the base. Form a mask over the top surface of the conductive metal layer with C solder bump openings therethrough with the shape of C solder bump images down to the surface of the conductive metal layer above the contacts. Etch away the exposed portions of the conductive metal layer below the C solder bump openings to form through holes in the conductive metal layer exposing C solder bump plating sites on the top surface of the base below the C solder bump openings with the conductive metal layer remaining intact on the periphery of the through holes at the C solder bump plating sites. As an option, form a barrier layer over the plating sites next. Form C solder bumps on the plating sites on the base/barrier layer within the C solder bump openings, with the C solder bumps being in contact with the conductive metal layer on the periphery of the through holes.

US Patent:

6661100, Dec 9, 2003

Filed:

Jul 30, 2002

Appl. No.:

10/210631

Inventors:

Brent A. Anderson - Jericho VT
Randolph F. Knarr - Goldens Bridge NY
Sarah H. Knickerbocker - Hopewell Junction NY
Edmund J. Sprogis - Underhill VT
Kamalesh K. Srivastava - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257784, 257778, 257723, 257777, 257691

Abstract:

A low impedance power distribution structure and method for substrate packaging of semiconductor chips containing very large scale integrated circuit (VLSI) circuits, such as microprocessors and associated memory, is presented. The power distribution structure incorporates under bump metallurgy (UBM) solder bump forming technology to produce not only solder bump connections that are vertically oriented, but also low impedance distribution wires that are horizontally oriented, and which provide electrical interconnection between various selected electrical contact points, such as solder bumps. These low impedance distribution wires introduce the benefits of low characteristic impedance to the substrates power distribution structure.

US Patent:

6727589, Apr 27, 2004

Filed:

Nov 30, 2000

Appl. No.:

09/725862

Inventors:

Stephen E. Greco - LaGrangeville NY
John P. Hummel - Millbrook NY
Joyce Liu - Hopewell Junction NY
Vincent J. McGahay - Poughkeepsie NY
Rebecca Mih - Wappingers Falls NY
Kamalesh Srivastava - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257751, 257750, 257752, 257758, 257642, 257643, 257774, 257761, 257762, 257763, 257764, 257765, 257766

Abstract:

A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.

US Patent:

6995084, Feb 7, 2006

Filed:

Mar 17, 2004

Appl. No.:

10/708649

Inventors:

Kamalesh K. Srivastava - Wappingers Falls NY, US
Subhash L. Shinde - Courtlandt Manor NY, US
Tien-Jen Cheng - Bedford NY, US
Sarah H. Knickerbocker - Hopewell Junction NY, US
Roger A. Quon - Rhinebeck NY, US
William E. Sablinski - Beacon NY, US
Julie C. Biggs - Wappingers Falls NY, US
David E. Eichstadt - Park Ridge IL, US
Jonathan H. Griffith - Lagrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438613, 438614

Abstract:

A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.

US Patent:

6995475, Feb 7, 2006

Filed:

Sep 18, 2003

Appl. No.:

10/666775

Inventors:

Julie C. Biggs - Wappingers Falls NY, US
Tien-Jen Cheng - Bedford NY, US
David E. Eichstadt - North Salem NY, US
Lisa A. Fanti - Hopewell Junction NY, US
Jonathan H. Griffith - Poughkeepsie NY, US
Randolph F. Knarr - Goldens Bridge NY, US
Sarah H. Knickerbocker - Hopewell Junction NY, US
Kevin S. Petrarca - Newburgh NY, US
Roger A. Quon - Beacon NY, US
Wolfgang Sauter - Richmond VT, US
Kamalesh K. Srivastava - Wappingers Falls NY, US
Richard P. Volant - New Fairfield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257784, 257737, 257761, 257766

Abstract:

A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.