Joseph F Salfelder

US Patent:

7040966, May 9, 2006

Filed:

Apr 16, 2004

Appl. No.:

10/825849

Inventors:

Joseph F. Salfelder - Pleasant Valley NY, US
Wayne Swart - Tivoli NY, US
Gopalakrishna B. Prabhu - San Jose CA, US
Srinivas R. Mirmira - San Jose CA, US
Laertis Economikos - Wappingers Falls NY, US
Fen Fen Jamin - Wappingers Falls NY, US
Donald J. Delehanty - Wappingers Falls NY, US
Daniel Heenan - North East MD, US
Joseph M. Danza - Newburgh NY, US

Assignee:

Applied Materials - Santa Clara CA
International Business Machine Corporation - Armonk NY

International Classification:

B24B 1/00

US Classification:

451 41, 451285, 451287, 438691

Abstract:

A method and polishing system for planarizing a substrate having one or more materials formed thereon. The method generally includes positioning the substrate in proximity with a polishing pad, dispensing a polishing fluid to the polishing pad, the polishing fluid being subjected to carbonation prior to being dispensed to the polishing pad, and polishing the substrate. The polishing system generally includes a polishing platen having a polishing pad disposed thereon and in proximity to the substrate, a controller configured to cause the polishing pad to contact the substrate, and a polishing fluid delivery system to deliver a polishing fluid to the polishing pad, the polishing fluid delivery system including a carbonation system.

US Patent:

56318030, May 20, 1997

Filed:

Jan 6, 1995

Appl. No.:

8/369237

Inventors:

John F. Cameron - Los Altos CA
Joseph F. Salfelder - Williston VT
Chandra Deshpandey - Fremont CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H02N 1300

US Classification:

361234

Abstract:

An electrostatic chuck (20) for holding a substrate (40) in a process chamber (50) comprises a base (25) supporting a resilient insulator (30). The insulator (30) comprises (i) an electrode (35) embedded therein; (ii) a top surface (34) with a peripheral edge (32); and (iii) cooling grooves (45) for holding coolant in the top surface (34), the tips (125) of the cooling grooves (45) and the peripheral edge (32) of the insulator (30) defining an edge gap (130) having a width w. The width w of the edge gap (130) is sized sufficiently small that the coolant in the grooves (45) cools the perimeter (120) of the substrate (40) held on the chuck (20). The insulator (30) is sufficiently thick that when a substrate (40) is electrostatically held on the chuck (20) and coolant is held in the cooling grooves (45), the insulator (30) in the edge gap (130) resiliently conforms to the substrate (40) so that substantially no coolant leaks out from the tips (125) of the cooling grooves (45). Preferably, the coolant grooves (45) do not cut into the electrode (35).

US Patent:

56360983, Jun 3, 1997

Filed:

May 11, 1995

Appl. No.:

8/439010

Inventors:

Joseph Salfelder - Williston VT
Dennis Grimard - Ann Arbor MI
John F. Cameron - Los Altos CA
Chandra Deshpandey - Fremont CA
Robert Ryan - Sunnyvale CA
Michael G. Chafin - Underhill VT

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H02N 1300

US Classification:

361234

Abstract:

An erosion resistant electrostatic chuck 20 for holding a substrate 45 having a peripheral edge 50, in an erosive environment, comprises an electrostatic member 25 including (i) an electrode 30, and (ii) an insulator 35 covering the electrode. A barrier 55 is circumferentially disposed about the electrostatic member 25. The barrier 55 comprises a first contact surface 60 capable of being pressed against the peripheral edge 50 of the substrate 45 to form a seal around the substrate 45 to reduce exposure of the electrostatic member 25 of the chuck 20 to the erosive environment.

US Patent:

20220310531, Sep 29, 2022

Filed:

Mar 26, 2021

Appl. No.:

17/214411

Inventors:

- Santa Clara CA, US
Lan Yu - Albany NY, US
Joseph F. Salfelder - Pleasant Valley NY, US
Ki Cheol Ahn - Watervliet NY, US
Tyler Sherwood - Fonda NY, US
Siddarth Krishnan - San Jose CA, US
Michael Jason Fronckowiak - Troy NY, US
Xing Chen - Dublin CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 23/00
H01L 21/311
H01L 21/308
H01L 21/304

Abstract:

Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.

US Patent:

20220223402, Jul 14, 2022

Filed:

Jan 14, 2021

Appl. No.:

17/149399

Inventors:

- Santa Clara CA, US
Benjamin D. Briggs - Clifton Park NY, US
Tyler Sherwood - Fonda NY, US
Raghav Sreenivasan - Fremont CA, US
Joseph Salfelder - Pleasant Valley NY, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/02
H01L 21/4757

Abstract:

Processing methods may be performed to form a filled contact hole in a mirror layer of a semiconductor substrate. The method may include forming a contact hole through a mirror layer of the semiconductor substrate by an etch process. The method may include filling the contact hole with a fill material. A portion of the fill material may overlie the mirror layer. The method may also include removing a portion of the fill material external to the contact hole by chemical mechanical polishing landing on the mirror layer.

US Patent:

20230066610, Mar 2, 2023

Filed:

Aug 25, 2021

Appl. No.:

17/411599

Inventors:

- Santa Clara CA, US
Joseph F. Salfelder - Pleasant Valley NY, US
Ki Cheol Ahn - Watervliet NY, US
Kai Ma - Palo Alto CA, US
Raghav Sreenivasan - Fremont CA, US
Jason Appell - Malta NY, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 23/00

Abstract:

Methods of semiconductor processing may include contacting a substrate with a first slurry and a first platen. The substrate may include silicon oxide defining one or more features, a liner extending across the silicon oxide and within the one or more features, and a copper-containing layer deposited on the liner and extending within the one or more features. The first slurry and the first platen may remove a first portion of the copper-containing layer. The methods may include contacting the substrate with a second slurry and a second platen, which may remove at least a portion of the liner. The methods may include contacting the substrate with a third slurry and a third platen, which may remove a second portion of the copper-containing layer. The methods may include contacting the substrate with a fourth slurry and a fourth platen, which may remove at least a portion of the silicon oxide.