Joseph Anthony Perrie

US Patent:

20070005322, Jan 4, 2007

Filed:

Jun 30, 2005

Appl. No.:

11/171725

Inventors:

Aaron Patzer - Austin TX, US
Joseph Perrie - Austin TX, US
Steven Roberts - Cedar Park TX, US
Todd Swanson - Round Rock TX, US

International Classification:

G06F 17/50

US Classification:

703014000

Abstract:

Hardware logic for generating breakpoint signals (basic events) based on state changes in observed (“tagged”) hardware resource of a design under test is automatically generated and added to the simulation model of the design under test. A switch/network is included in the model for mapping basic events to complex breakpoint logic. Complex breakpoints combine basic events to form more complex breakpoints that can be selectively enabled/disabled by the simulation user. In one embodiment, user settable values are compared with complex breakpoint values to further define a complex breakpoint.

US Patent:

20070005323, Jan 4, 2007

Filed:

Jun 30, 2005

Appl. No.:

11/171760

Inventors:

Aaron Patzer - Austin TX, US
Joseph Perrie - Austin TX, US
Steven Roberts - Cedar Park TX, US
Todd Swanson - Round Rock TX, US

International Classification:

G06F 17/50

US Classification:

703014000

Abstract:

Hardware logic for generating breakpoint signals based on state changes in observed (“tagged”) hardware resource of a design under test is automatically generated and added to the simulation model of the design under test. These breakpoints halt simulation when a user programmable event, such as an assertion, test-case failure, or trigger occurs. Allowing the end-user to define the register values used in comparison to or timing of tagged resources, results in breakpoints that can be created, changed, enabled, or disabled without rebuilding the simulation model. Because the breakpoint logic is in-circuit, it takes full advantage of the acceleration made possible by hardware simulators, while providing an interactive environment for both functional hardware verification and software development on the simulated hardware mode.

US Patent:

20080126068, May 29, 2008

Filed:

Aug 11, 2006

Appl. No.:

11/464122

Inventors:

Clark M. O'Niell - White Plains NY, US
Joseph A. Perrie - Austin TX, US
Steven L. Roberts - Cedar Park TX, US
Christopher J. Spandikow - Austin TX, US

International Classification:

G06F 9/455

US Classification:

703 20

Abstract:

A cache replacement system for extending the debugging capabilities of accelerated simulation by enabling enhanced cache data and state checking is provided. The system includes a Cell Broadband Engine Architecture (CBEA) compliant system implementing Replacement Management Tables in an accelerated simulation environment. The RMTs control cache replacement and allow the software to direct entries with specific address ranges at a particular subset of the cache. The RMTs further allow for locking data in the cache and are utilized to prevent overwriting data in the cache by directing data that is known to be used only once at a particular set. Using the locking mechanism in an accelerated simulation environment, a user is able to run code sets, which, when the microprocessor system being tested is correctly designed, generates identical and verifiable data and cache states in each of the different sets of the cache.

US Patent:

20080167854, Jul 10, 2008

Filed:

Jan 9, 2007

Appl. No.:

11/621335

Inventors:

Sanjay Gupta - Austin TX, US
Joseph Anthony Perrie - Austin TX, US
Steven Leonard Roberts - Cedar Park TX, US
Todd Swanson - Round Rock TX, US

International Classification:

G06F 9/455

US Classification:

703 28

Abstract:

A system and method for incorporating design behavior and external stimulus in microdevice model feedback using a shared memory is presented. The invention describe herein uses the attached memory model to provide additional heuristics to an application executing on an emulation system's device model, which results in a more detail and real-life device emulation. The attached memory model provides a storage area for a runtime software environment to store emulation data, which is subsequently provided to the device model during emulation. The emulation data may include 1) randomization stimuli to the device model, 2) additional runtime data for checking heuristics, and 3) emulation data points that are otherwise not accessible to the device model.

US Patent:

20060052997, Mar 9, 2006

Filed:

Sep 9, 2004

Appl. No.:

10/937694

Inventors:

Adam Patrick Burns - Austin TX, US
Joseph Anthony Perrie - Austin TX, US
Steven Leonard Roberts - Cedar Park TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45

US Classification:

703022000

Abstract:

The present invention provides for automating identification of critical regions in memory. A behavioural software reference model of an operating system is certified as substantially error free. The behavioural software reference model is run of operating system. At least one access pattern of the behavioural software reference model is monitored. A cycle accurate software reference model of operating system is run. At least one access pattern of the cycle accurate software reference model is monitored. The at least one access pattern of the behavioural software reference model is compared with the at least one access pattern of the cycle accurate software reference model, thereby allowing a time saving in the testing process.