Joseph Thinh Nguyen

US Patent:

6574599, Jun 3, 2003

Filed:

Mar 31, 1999

Appl. No.:

09/283772

Inventors:

Kang S. Lim - Danville CA
Joseph A. Nguyen - Pacific Grove CA

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G10L 1522

US Classification:

704270, 704275, 379 8801, 379 8803

Abstract:

A method for permitting a user to create a plurality of outbound communication paths to a plurality of communication devices from a unified messaging system, the creating the plurality of the outbound communication paths being performed responsive to verbal input from a user through a telephone. The method includes receiving at the unified messaging system the verbal input from the user through the telephone. There is also included recognizing an action word from the verbal input which includes an action word and called party identity or contacting data. An calendar database for the callee, external to the callers unified messaging system, is accessed via a network to determine whether a calendar entry therein temporally overlaps a time of the verbal command creating the end-to-end connection. The ascertained availability information may be provided to the caller for input whether to contact the callee. A conjunctive word with the identity or contacting data for a second callee may also be verbally input before the call table is finalized.

US Patent:

6751214, Jun 15, 2004

Filed:

Mar 30, 2000

Appl. No.:

09/539478

Inventors:

Bidyut Parruck - Cupertino CA
Joseph A. Nguyen - San Jose CA
Chulanur Ramakrishnan - Saratoga CA

Assignee:

Azanda Network Devices, Inc. - Sunnyvale CA

International Classification:

H04J 324

US Classification:

370352, 3703954, 370471, 370474, 370535, 398 43

Abstract:

A method for dynamically allocating bandwidth among ATM cells and packets scheduled for output from an aggregation multiplexer of a transport-layer device configured to multiplex both ATM cells and packets onto the same channel of an optical fiber. The method includes local control and relative priority lookup of incoming ATM cells and packets to support output decision. When compared to currently employed methods, the required level of coordination with the receiving circuit for dynamic bandwidth allocation is substantially lower, thereby reducing operational complexity for network operators and latency for critical data when reallocating bandwidth.

US Patent:

6751224, Jun 15, 2004

Filed:

Mar 30, 2000

Appl. No.:

09/539477

Inventors:

Bidyut Parruck - Cupertino CA
Joseph A. Nguyen - San Jose CA
Chulanur Ramakrishnan - Saratoga CA

Assignee:

Azanda Network Devices, Inc. - Sunnyvale CA

International Classification:

H04L 1264

US Classification:

3703956, 370466, 370474

Abstract:

An integrated ATM/packet segmentation-and-reassembly engine for handling both packet and ATM input data and outputting packets containing information from both the packet and ATM input data. The integrated ATM/packet segmentation-and-reassembly engine is also configured for receiving packets containing information destined for transmission as ATM cells and information destined for transmission as packets, perform the segregation function and segmentation function on the information destined for transmission as ATM cells in order to output both ATM cells and packets. Architecture includes the ability to output both ATM cells and packets on a single optical fiber.

US Patent:

6810039, Oct 26, 2004

Filed:

Mar 30, 2000

Appl. No.:

09/539476

Inventors:

Bidyut Parruck - Cupertino CA
Joseph A. Nguyen - San Jose CA
Chulanur Ramakrishnan - Saratoga CA

Assignee:

Azanda Network Devices, Inc. - Sunnyvale CA

International Classification:

H04L 1256

US Classification:

3703955, 370466, 370474

Abstract:

A processor-based architecture having a processor for facilitating transmission between an ATM port, a first packet port, and a second packet port. The processor-based architecture includes random access memory and a processor coupled to the random access memory and configured to receive ATM cells from the ATM port and first packets from the first packet port and for outputting second packets containing information from both the ATM cells and the first packets on the second packet port. The processor-based architecture includes segmentation-and-reassembly to facilitate bi-directional packet-to-ATM translation functionality. In one embodiment, the processor-based architecture is implemented on a single card and includes dynamic traffic management between ATM and packet traffic.

US Patent:

6874224, Apr 5, 2005

Filed:

Jun 21, 2002

Appl. No.:

10/175888

Inventors:

Rajendra Ahuja - Fremont CA, US
Joseph Nguyen - San Jose CA, US
Mostafa Jafarnia - Fremont CA, US

Assignee:

Waukesha Electric Systems, Inc. - Waukesha WI

International Classification:

H01F007/06

US Classification:

29606, 296021, 29832, 29854, 338 12

Abstract:

A three phase transformer circuit is provided that includes a supply side, wherein the supply side is selectably configurable, via the use of se of terminal boards, between a delta connection and a wye connection at a time of use and, a load side, wherein the load side is selectably configurable between a delta connection and a wye connection at the time of use. The three-phase transformer also provides for selecting an input voltage, from multiple input voltages, via the sets of terminal boards, at the time of use, and for selecting an output voltage for the supply side, from multiple output voltage, at the time of use.

US Patent:

6965603, Nov 15, 2005

Filed:

Mar 20, 2000

Appl. No.:

09/528802

Inventors:

Bidyut Parruck - Cupertino CA, US
Joseph A. Nguyen - San Jose CA, US
Chulanur Ramakrishnan - Saratoga CA, US

Assignee:

Cortina Systems, Inc. - Mountain View CA

International Classification:

H04L012/56

US Classification:

3703955, 370466

Abstract:

An architecture for transmitting both ATM cells and data packets via a single optical fiber and for receiving ATM cells and data packets via a single optical fiber. The architecture includes both a transmission convergence device (TCD) circuit and a segmentation-and-reassembly (SAR) circuit and is implemented as integrated circuits, preferably as part of a router to eliminate the need for a SONET multiplexer.

US Patent:

7095760, Aug 22, 2006

Filed:

Mar 30, 2000

Appl. No.:

09/539461

Inventors:

Bidyut Parruck - Cupertino CA, US
Joseph A. Nguyen - San Jose CA, US
Chulanur Ramakrishnan - Saratoga CA, US

Assignee:

Cortina Systems, Inc. - Mountain View CA

International Classification:

H04J 3/02

US Classification:

370539, 37039552

Abstract:

A technique for disguising ATM cells as ATM cell-containing packets within a routing facility to permit the packet-only switch to also handle switching of the ATM cells. The technique has wide applications within the backbone infrastructure, Wide Area Networks, Metro Area Networks, Local Area Networks, and particularly within a routing facility to handle high speed traffic. The technique can receive both ATM cells and packets for switching via a single channel or optical fiber or receive ATM cells and packets via two separate channels or two separate fibers. The ability to handle both ATM cell and packet switching allows packet-only routers to handle ATM traffic, thereby reducing the cost of the switching infrastructure for network operators.

US Patent:

7145910, Dec 5, 2006

Filed:

Jun 15, 2004

Appl. No.:

10/869379

Inventors:

Bidyut Parruck - Cupertino CA, US
Joseph A. Nguyen - San Jose CA, US
Chulanur Ramakrishnan - Saratoga CA, US

Assignee:

Cortina Systems, Inc. - Mountain View CA

International Classification:

H04J 3/24
H04L 12/56

US Classification:

3703951, 370471, 370474

Abstract:

A method for dynamically allocating bandwidth among ATM cells and packets scheduled for output from an aggregation multiplexer of a transport-layer device configured to multiplex both ATM cells and packets onto the same channel of an optical fiber. The method includes local control and relative priority lookup of incoming ATM cells and packets to support output decision. When compared to currently employed methods, the required level of coordination with the receiving circuit for dynamic bandwidth allocation is substantially lower, thereby reducing operational complexity for network operators and latency for critical data when reallocating bandwidth.