Joseph E Mathis

US Patent:

51558076, Oct 13, 1992

Filed:

Sep 14, 1990

Appl. No.:

7/582823

Inventors:

Ballard J. Blevins - Lexington KY
William G. Kulpa - Austin TX
Joseph R. Mathis - Georgetown TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

395200

Abstract:

A system for transferring data between a pair of data processing units having system buses includes a plurality of memories in each of the data processing units; each memory having a random access portion and an associated sequential access portion; means for transferring data between each of the random access portions of each of the memories and its associated sequential access portion; and means connecting the sequential access portions of each of the memories in one of the data processing units to the sequential access portions of the other of said data processing units to permit data flow therebetween; the data flow between the sequential access portions of said memories occurring asynchronously of the remainder of the system so that the data processing units can utilize their system buses during such data flow.

US Patent:

46959483, Sep 22, 1987

Filed:

Feb 28, 1985

Appl. No.:

6/706734

Inventors:

Ballard J. Blevins - Lexington KY
William G. Kulpa - Austin TX
Joseph R. Mathis - Georgetown TX
John W. McCullough - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1210

US Classification:

364200

Abstract:

An improvement in a bus converter that provides a bus to bus address translation function permitting access from an I/O device connected on the I/O bus to a system bus and system memory, where the bus converter includes a circuit connected to the I/O bus to partition I/O addresses received from the I/O bus into a lower order field and a high order field and connected to a circuit to receive DMA ID's from the I/O bus to combine this DMA ID with the high order field to form a first combined address. The first combined address is input to a memory which provides corresponding control field and prefix field data. An address formatter is further included that is connected to receive the control field and prefix field data from the memory and further connected to receive the low order address field. The address formatter forms a second combined address from the prefix field, control field and lower order address field. This second combined address is then provided to a system bus to permit access to the system bus.