Joseph M Kulinets

US Patent:

6696910, Feb 24, 2004

Filed:

Jul 12, 2001

Appl. No.:

09/904014

Inventors:

Peter R. Nuytkens - Melrose MA
Ilya E. Popeko - Forest Hills NY
Joseph M. Kulinets - Stamford CT

Assignee:

Custom One Design, Inc. - Melrose MA

International Classification:

H01F 500

US Classification:

336200, 336232, 336223, 296021

Abstract:

A printed circuit board has two layers of printed circuit board dielectric material; a core made of ferromagnetic material between the two layers; and conductive leads on the opposite side of each dielectric layer from the core connected by via holes through both dielectric layers to form a conducting coil around the core. The conductive leads can form two separate coils around the core to form a transformer. A planar conducing sheet can be placed on or between one or more of the printed circuit boards dielectric layers to shield other circuitry on the printed circuit board from magnetic fields generated around the core. The core can be formed at least in part by electroless plating. Electroplating can be used to add a thicker layer of less conductive ferromagnetic material. Ferromagnetic inductive cores can be formed on the surface of a dielectric material by: dipping the surface of the dielectric in a solution containing catalytic metal particles having a slight dipole; and placing the dielectric in a metal salt to cause a layer containing metal to be electrolessly plated upon the dielectric. Plasma etching or other technique can be used before the dipping process to roughen the dielectrics surface to help attract the catalytic particles.

US Patent:

6838750, Jan 4, 2005

Filed:

Jul 12, 2001

Appl. No.:

09/904306

Inventors:

Peter R. Nuytkens - Melrose MA, US
Ilya E. Popeko - Forest Hills NY, US
Joseph M. Kulinets - Stamford CT, US

Assignee:

Custom One Design, Inc. - Melrose MA

International Classification:

H01L 23495

US Classification:

257666, 257667, 257668, 257635, 257758, 257700, 257324

Abstract:

An electrical circuit having one or more dielectric layers formed of latex; and one or more layers of electrically conductive material, such as copper, patterned to form multiple electrical interconnects, with each such layer placed on top of one of said dielectric layers. The dielectric and conductive layers can be used to connect multiple chips in a multichip module. The latex layers can be formed to have a top surface that contains peaks and valleys, and the conductive layers can be formed of a first metal that substantially fills such valleys, so as to increase the adherence of the metal to the latex surface. The layers of conductive metal can contain particles of a second metal between said peaks and valleys of the latex layer that were used as a catalytic seed particles to promote the deposition of the metal layer onto the top surface of the latex.

US Patent:

7179742, Feb 20, 2007

Filed:

Dec 13, 2004

Appl. No.:

11/010790

Inventors:

Peter R. Nuytkens - Melrose MA, US
Ilya E. Popeko - Forest Hills NY, US
Joseph M. Kulinets - Stamford CT, US

Assignee:

Custom One Design, Inc. - Melrose MA

International Classification:

H01L 21/44

US Classification:

438678, 438687, 257666

Abstract:

Methods of electroless plating metal on a dielectric material includes dipping the dielectric in a solution containing attractive catalytic metal particles and a metal salt solution. A thicker metallic layer can be deposited on top of the resulting layer by electroplating. Electrical circuits and multichip modules including such circuits can be formed having one or more dielectric layers comprised of latex and one or more layers of conductive leads, one or more dielectric layers comprised of a flexible dielectric material, and one or more layers of electrically conductive material patterned to interconnect such ICs. Frames that hold ICs against a substrate may be employed to planarize their top surfaces against the substrate, as well as standard photolithographic techniques in creating conductive paths on the dielectric material between the ICs.

US Patent:

7231707, Jun 19, 2007

Filed:

Feb 23, 2004

Appl. No.:

10/784324

Inventors:

Peter R. Nuytkens - Melrose MA, US
Ilya E. Popeko - Forest Hills NY, US
Joseph M. Kulinets - Stamford CT, US

Assignee:

Custom One Design, Inc. - Melrose MA

International Classification:

H01F 7/06

US Classification:

29606, 296021, 29607, 29829, 29832, 205119, 205122, 216 67, 336 20, 336212, 336223, 336232, 427 995

Abstract:

Method of forming a ferromagnetic layer on at least one surface of a dielectric material that may be serve as an inductive core on a printed circuit board or a multichip module. Conductive leads can form two separate coils around the core to form a transformer, and a planar conducing sheet can be placed on or between one or more of the dielectric layers as magnetic shielding. The core can be formed at least in part by electroless plating, and electroplating can be used to add a thicker layer of less conductive ferromagnetic material. Ferromagnetic layers are formed by dipping the dielectric surface in a solution containing catalytic metal particles having a slight dipole, and placing the surface in a metal salt to cause a layer containing metal to be electrolessly plated upon the dielectric. Surface roughening techniques can be used before the dipping to help attract the catalytic particles.

US Patent:

7449412, Nov 11, 2008

Filed:

Feb 15, 2007

Appl. No.:

11/706812

Inventors:

Peter R. Nuytkens - Melrose MA, US
Ilya E. Popeko - Forest Hills NY, US
Joseph M. Kulinets - Stamford CT, US

Assignee:

Custom One Design, Inc. - Melrose MA

International Classification:

H01L 21/44

US Classification:

438678, 438398, 438687, 257666, 257690

Abstract:

Methods of electroless plating metal on a dielectric material includes dipping the dielectric in a solution containing attractive catalytic metal particles and a metal salt solution. A thicker metallic layer can be deposited on top of the resulting layer by electroplating. Electrical circuits and multichip modules including such circuits can be formed having one or more dielectric layers comprised of latex and one or more layers of conductive leads, one or more dielectric layers comprised of a flexible dielectric material, and one or more layers of electrically conductive material patterned to interconnect such ICs. Frames that hold ICs against a substrate may be employed to planarize their top surfaces against the substrate, as well as standard photolithographic techniques in creating conductive paths on the dielectric material between the ICs.

US Patent:

7557742, Jul 7, 2009

Filed:

Dec 20, 2007

Appl. No.:

11/961960

Inventors:

Joseph M. Kulinets - North Andover MA, US
Peter R. Nuytkens - Melrose MA, US
Oleg Korobeynikov - Swampscott MA, US

Assignee:

Custom One Design, Inc. - Melrose MA

International Classification:

H03M 3/00

US Classification:

341143, 341155

Abstract:

Methods and apparatus for the conversion of analog signals into digital signals using second order or higher sigma-delta modulators in pipelined or cyclic architectures.

US Patent:

20080100393, May 1, 2008

Filed:

May 2, 2005

Appl. No.:

11/579005

Inventors:

Peter R. Nuytkens - Melrose MA, US
Joseph M. Kulinets - Stamford CT, US

Assignee:

Custom One Design, Inc. - Melrose MA

International Classification:

H04L 27/12
G05F 1/00
H03K 3/36
H04B 1/38
H02J 1/00

US Classification:

332100, 323282, 307 80, 331 46, 455 73

Abstract:

A direct conversion RF transceiver () and ASIC having an on-chip voltage controlled oscillator operating frequency that is half of the transmitter () and/or receiver () operating frequency, the VCO () being comprised of a plurality of synchronized LC oscillators (A-D) introducing precise phase shifts that eliminate frequency ambiguity. The transceiver incorporates several low power circuits, including on-chip a power converter switchably coupling a capacitor () to a power supply () and to an electrical load (), multiple switchable low dropout regulators (A, B) each coupled to alternate power supplies () and having electrical components (A, B) for setting the bandwidth of the respective low dropout regulator. The transceiver also includes a FSK digital modulator utilizing a circuit-implemented polynomial piecewise approximation () of a raised cosine signal.

US Patent:

20080157295, Jul 3, 2008

Filed:

Dec 20, 2007

Appl. No.:

11/961984

Inventors:

Peter R. Nuytkens - Melrose MA, US
Noureddine Hawat - Woburn MA, US
Joseph M. Kulinets - North Andover MA, US

Assignee:

Custom One Design, Inc. - Melrose MA

International Classification:

H01L 23/498
H01L 21/98

US Classification:

257659, 257686, 438109, 257E23063, 257E21705

Abstract:

Methods and apparatus for multichip modules having improved shielding and isolation properties.