Joseph D Gutierrez

US Patent:

53882261, Feb 7, 1995

Filed:

Oct 5, 1992

Appl. No.:

7/956194

Inventors:

Joseph A. Gutierrez - Austin TX
William C. Moyer - Dripping Springs TX
Yui K. Ho - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1202

US Classification:

395325

Abstract:

A method and apparatus for accessing a register in a data processing system (10). In one form, the present invention uses a storage circuit (23) to act as a register copy (23) of the original register (33). An access to the register location may actually selectively access the original register (33), the register copy (23), or both the original register (33) and the register copy (23). Register select logic (70) is used to perform this selection function. Register select logic (70) may also be used to keep track of the current status of the contents of the original register (33) and of the contents of the register copy (23). Register select logic (70) may also monitor the internal state of data processing system (10).

US Patent:

53197631, Jun 7, 1994

Filed:

Apr 2, 1991

Appl. No.:

7/679463

Inventors:

Yui K. Ho - Austin TX
William C. Moyer - Dripping Springs TX
Joseph A. Gutierrez - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 922
G06F 926
G06F 1118
G06F 1330

US Classification:

395425

Abstract:

A data processing system (10) implements a static and a dynamic masking operation of operand information concurrently. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison operation between the breakpoint address stored in a breakpoint register (24) and a logical address transferred via a logical address bus (11). A dynamic mask value implements a variable mask which allows the data processing system to mask the breakpoint address according to the size of a breakpoint address access. The static mask value and the dynamic mask value are concurrently implemented using a specialized bit cell (60) contained in both the breakpoint register (24) and the CAM array (26). The specialized bit cell (60) is comprised of two transistors (62 and 64) to concurrently mask a respective bit of operand information during a comparison operation.

US Patent:

52396428, Aug 24, 1993

Filed:

Apr 2, 1991

Appl. No.:

7/679477

Inventors:

Joseph A. Gutierrez - Austin TX
William C. Moyer - Dripping Springs TX
Yui K. Ho - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1100
G06F 1202
G11C 800

US Classification:

395425

Abstract:

A data processing system (10) implements a combined static and a dynamic masking operation of a breakpoint address. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison operation between the breakpoint address stored in a breakpoint register (24) and a logical address transferred via a logical address bus (11). A dynamic mask value implements a variable mask which allows the data processing system to mask the breakpoint address according to the size of a breakpoint address access. The static mask value and the dynamic mask value are combined using the same circuitry to form a combined mask value (19). Breakpoint function and address translation are implemented in the system (10) by using the same drive and control circuitry (20,44,48) to accomplish both functions. The breakpoint register (24) is implemented as an entry in a CAM array (26).

US Patent:

57324050, Mar 24, 1998

Filed:

Nov 8, 1994

Appl. No.:

8/336702

Inventors:

Yui Kaye Ho - Austin TX
William C. Moyer - Dripping Springs TX
Joseph A. Gutierrez - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1204

US Classification:

711 3

Abstract:

A method and apparatus for performing a cache operation in a data processing system (10). In one form, the present invention has a "block address translation cache (BATC) only mode" in which a received logical address is compared to the logical addresses stored in only one of a plurality of address translation caches, i. e. the block address translation cache (BATC) (76). The overhead associated with loading and comparing one or more other caches (78) is not incurred. If the comparison with that one cache (BATC) (76) produces a hit, that cache (BATC) (76) supplies the address that is used as the physical address. If the comparison with that one cache (BATC) (76) produces a miss, then a 1:1 mapping is used and the received logical address is used as the physical address.

US Patent:

53415000, Aug 23, 1994

Filed:

Apr 2, 1991

Appl. No.:

7/679478

Inventors:

William C. Moyer - Dripping Springs TX
Joseph A. Gutierrez - Austin TX
Yui K. Ho - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1134

US Classification:

395725

Abstract:

A data processing system (10) implements a combined static and a dynamic masking operation of a breakpoint address. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison operation between the breakpoint address stored in a breakpoint register (24) and a logical address transferred via a logical address bus (11). A dynamic mask value implements a variable mask which allows the data processing system to mask the breakpoint address according to the size of a breakpoint address access. The static mask value and the dynamic mask value are combined using the same circuitry to form a combined mask value (19). Breakpoint function and address translation are implemented in the system (10) by using the same drive and control circuitry (20, 44, 48) to accomplish both functions. The breakpoint register (24) is implemented as an entry in a CAM array (26).