John Rfs Szeto

US Patent:

56511248, Jul 22, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/478025

Inventors:

Gene W. Shen - Mountain View CA
John Szeto - Oakland CA
Niteen A. Patkar - Sunnyvale CA
Michael C. Shebanow - Plano TX
Michael A. Simone - Santa Clara CA

Assignee:

HAL Computer Systems, Inc. - Campbell CA

International Classification:

G06F 1100

US Classification:

395391

Abstract:

Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded instruction attributes. Such time-out conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, and such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional checkpoints, or in a novel logical and physical register rename map checkpointing technique. Timeout checkpoint formation may be used with conventional processor backup techniques as well as with a novel backtracking technique including processor backup and backstepping.

US Patent:

56597215, Aug 19, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/476419

Inventors:

Gene W. Shen - Mountain View CA
John Szeto - Oakland CA
Niteen A. Patkar - Sunnyvale CA
Michael C. Shebanow - Plano TX

Assignee:

HAL Computer Systems, Inc. - Campbell CA

International Classification:

G06F 1100

US Classification:

395569

Abstract:

Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded instruction attributes. Such time-cut conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, and such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional. checkpoints, or in a novel logical and physical register rename map checkpointing technique.

US Patent:

56734263, Sep 30, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/484795

Inventors:

Gene W. Shen - Mountain View CA
John Szeto - Oakland CA
Michael C. Shebanow - Plano TX

Assignee:

HaL Computer Systems, Inc. - Cambell CA

International Classification:

G06F 746

US Classification:

395591

Abstract:

An out of program control order execution data processor that comprises an issue unit, execution means, a floating point exception unit a precise state unit, a floating point status register, and writing means. The issue unit issues instructions in program control order for execution. The issued instructions include floating point instructions and non-floating point instructions. The execution means executes the issued instructions such that at least the floating point instructions may be executed out of program control order by the execution means. The floating point exception unit includes a data storage structure including storage elements. Each issued instruction corresponds to one of the storage elements. Each storage element has a floating point instruction identifying field and a floating point trap type field. The floating point exception unit also includes first logic to write, for each issued instruction, data in the floating point instruction identifying field of the corresponding storage element which indicates whether or not the corresponding issued instruction is a floating point instruction.

US Patent:

56491360, Jul 15, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/483958

Inventors:

Gene W. Shen - Mountain View CA
John Szeto - Oakland CA
Niteen A. Patkar - Sunnyvale CA
Michael C. Shebanow - Plano TX

Assignee:

Hal Computer Systems, Inc. - Campbell CA

International Classification:

G06F 1100

US Classification:

395591

Abstract:

A high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring precise state at any instruction boundary; (3) tracking instruction status to maintain precise state; (4) checkpointing instructions to maintain precise state; (5) creating, maintaining, and using a time-out checkpoint; (6) tracking floating-point exceptions; (7) creating, maintaining, and using a watchpoint for plural, simultaneous, unresolved-branch evaluation; and (9) increasing processor throughput while maintaining precise state.

US Patent:

57519854, May 12, 1998

Filed:

Jun 7, 1995

Appl. No.:

8/487801

Inventors:

Gene W. Shen - Mountain View CA
John Szeto - Oakland CA
Niteen A. Patkar - Sunnyvale CA
Michael C. Shebanow - Plano TX

Assignee:

Hal Computer Systems, Inc. - Campbell CA

International Classification:

G06F 930

US Classification:

395394

Abstract:

Apparatus and method provide for tracking and maintaining precise state by assigning a unique identification tag to each instruction at the time of issue, associating the tag with a storage location in a first active instruction data structure, updating the data stored in the storage location in response to instruction activity status changes for each instruction, and maintaining a plurality of pointers to the storage locations that move in response to the instruction activity status. Status information includes an activity data item, such as an activity bit, that is set at the time the instruction is issued and cleared when execution completes without error. Pointers are established that point to the last issued instruction, the last committed instruction pointer, and reclaimed instruction pointer. These three pointers are moved forward toward the later issued (newer) instructions along the data structure based on comparisons of the active-bit for each location associated with one instruction in the data structure and predetermined rules. Exceptions or error conditions for any instruction prevent changing the active-bit so that movement of the pointers is controlled and prevented under these error conditions.

US Patent:

59665300, Oct 12, 1999

Filed:

Jun 11, 1997

Appl. No.:

8/872982

Inventors:

Gene W. Shen - Mountain View CA
John Szeto - Oakland CA
Niteen A. Patkar - Sunnyvale CA
Michael C. Shebanow - Plano TX

Assignee:

Fujitsu, Ltd.

International Classification:

G06F 1100

US Classification:

395591

Abstract:

A high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring state at any instruction boundary; (3) tracking instruction status; (4) checkpointing instructions; (5) creating, maintaining, and using a time-out checkpoint; (6) tracking floating-point exceptions; (7) creating, maintaining, and using a watchpoint for plural, simultaneous, unresolved-branch evaluation; and (9) increasing processor throughput while maintaining precise state. In one embodiment of the invention, a method of restoring machine state in a processor at any instruction boundary is disclosed. For any instruction which may modify control registers, the processor is either synchronized prior to execution or an instruction checkpoint is stored to preserve state; and for any instruction that creates a program counter discontinuity an instruction checkpoint is stored. Instruction execution status is monitored to detect a fault condition and if a fault occurs, the instruction identifier is saved according to predetermined rules and used as an endpoint to backup the program counter.

US Patent:

56447426, Jul 1, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/473223

Inventors:

Gene W. Shen - Mountain View CA
John Szeto - Oakland CA
Niteen A. Patkar - Sunnyvale CA
Michael C. Shebanow - Plano TX

Assignee:

Hal Computer Systems, Inc. - Campbell CA

International Classification:

G06F 1100

US Classification:

395591

Abstract:

Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded Instruction attributes. Such time-out conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, end such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional checkpoints, or in a novel logical and physical register rename map checkpointing technique. Timeout checkpoint formation may be used with conventional processor backup techniques as well as with a novel backtracking technique including processor backup and backstepping.