Joe R Trogolo from 23393 Stony Point Rd, Battle Lake, MN 56515, age 76, Phone: 218-864-5137

Us Patents

Transistors Formed With Grid Or Island Implantation Masks To Form Reduced Diffusion-Depth Regions Without Additional Masks And Process Steps
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US Patent:

6716709, Apr 6, 2004
Filed:

Dec 31, 2002
Appl. No.:

10/335322
Inventors:

Lily Springer - Dallas TX
Jeff Smith - Plano TX
Sheldon Haynie - Amherst NH
Joe R. Trogolo - Plano TX
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 21336
US Classification:

438301, 438270, 438279
Abstract:

A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.

Reduce 1/F Noise In Npn Transistors Without Degrading The Properties Of Pnp Transistors In Integrated Circuit Technologies
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US Patent:

6856000, Feb 15, 2005
Filed:

Oct 8, 2002
Appl. No.:

10/266476
Inventors:

Joe R. Trogolo - Plano TX, US
William Loftin - Plano TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L029/73
US Classification:

257518, 257525, 257588
Abstract:

An interfacial oxide layer () is formed in the emitter regions of the NPN transistor () and the PNP transistor (). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor () to reduce the 1/f noise in the NPN transistor.

System For High-Precision Double-Diffused Mos Transistors
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US Patent:

6867100, Mar 15, 2005
Filed:

Dec 19, 2002
Appl. No.:

10/326214
Inventors:

Henry L. Edwards - Garland TX, US
Sameer Pendharkar - Richardson TX, US
Joe Trogolo - Plano TX, US
Tathagata Chatterjee - Allen TX, US
Taylor Efland - Dallas TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L021/336
US Classification:

438266, 438279, 438301
Abstract:

The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (), and an oxide region () overlapping the moat region. A double-diffusion region () is formed within the oxide region, having end cap regions () that are effectively deactivated utilizing geometric and implant manipulations.

Transistors Formed With Grid Or Island Implantation Masks To Form Reduced Diffusion-Depth Regions Without Additional Masks And Process Steps
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US Patent:

6869851, Mar 22, 2005
Filed:

Jan 20, 2004
Appl. No.:

10/761438
Inventors:

Joe R. Trogolo - Plano TX, US
Lily Springer - Dallas TX, US
Jeff Smith - Plano TX, US
Sheldon Haynie - Amherst NH, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L021/336
H01L021/8836
US Classification:

438301, 438279, 438270
Abstract:

A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.

Reduce 1/F Noise In Npn Transistors Without Degrading The Properties Of Pnp Transistors In Integrated Circuit Technologies
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US Patent:

7195984, Mar 27, 2007
Filed:

Nov 22, 2004
Appl. No.:

10/994563
Inventors:

Joe R. Trogolo - Plano TX, US
William Loftin - Plano TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 21/339
US Classification:

438309, 257E21611
Abstract:

An interfacial oxide layer () is formed in the emitter regions of the NPN transistor () and the PNP transistor (). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor () to reduce the 1/f noise in the NPN transistor.

Versatile System For Optimizing Current Gain In Bipolar Transistor Structures
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US Patent:

7226835, Jun 5, 2007
Filed:

Jul 15, 2002
Appl. No.:

10/196634
Inventors:

Joe Trogolo - Plano TX, US
Tathagata Chatterlee - Richardson TX, US
Lily Springer - Dallas TX, US
Jeff Smith - Plano TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 31/0328
US Classification:

438235, 257197, 257198, 257565
Abstract:

Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure () and the required current density throughput of an electrical contact structure () are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.

Reliable High-Voltage Junction Field Effect Transistor And Method Of Manufacture Therefor
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US Patent:

7312481, Dec 25, 2007
Filed:

Oct 1, 2004
Appl. No.:

10/956863
Inventors:

Kaiyuan Chen - Dallas TX, US
Joe Trogolo - Plano TX, US
Tathagata Chatterjee - Allen TX, US
Steve Merchant - Bedford NH, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 29/74
H01L 29/423
H01L 31/111
US Classification:

257134, 257256, 257272, 257274, 257409, 257E29314
Abstract:

The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) () includes a well region () of a first conductive type located within a substrate () and a gate region () of a second conductive type located within the well region (), the gate region () having a length and a width. This embodiment further includes a source region () and a drain region () of the first conductive type located within the substrate () in a spaced apart relation to the gate region () and a doped region () of the second conductive type located in the gate region () and extending along the width of the gate region (). In place of or addition to the doped region (), the high-voltage junction field effect transistor (JFET) () may includes a conductive field plate () located over and extending along the width of the gate region ().

Method To Accurately Estimate The Source And Drain Resistance Of A Mosfet
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US Patent:

7595649, Sep 29, 2009
Filed:

Sep 25, 2007
Appl. No.:

11/860993
Inventors:

Tathagata Chatterjee - Allen TX, US
Joe R. Trogolo - Plano TX, US
Kaiyuan Chen - Dallas TX, US
Henry Litzmann Edwards - Garland TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

G01R 31/26
US Classification:

324719, 324769, 438 17
Abstract:

Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.