Jiunn-Yann Tsai

US Patent:

6495408, Dec 17, 2002

Filed:

Jan 4, 2000

Appl. No.:

09/477170

Inventors:

Shouli Hsia - San Jose CA
Jiunn-Yann Tsai - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 218238

US Classification:

438214, 438598, 257369

Abstract:

Disclosed is a process of electrically coupling the gate electrodes of an N-type transistor and a P-type transistor without causing substantial cross diffusion of P-type dopants into the N-type gate electrode and N-type dopants into the P-type gate electrode. This is possible because some or all annealing and diffusion steps are performed while the N-type and P-type gate electrodes are physically isolated from one another. Also disclosed is a Silicide as Diffusion Source process in which dopant atoms implanted in silicide regions diffuses out of the silicide regions and into the substrate to form source and drain diffusions. During this diffusion step adjacent N-type and P-type gate electrodes remain unconnected to prevent cross diffusion. Then, these two electrodes are electrically connected by a local interconnect. The local interconnection is a conductive path formed at about the level of the polysilicon (i. e.

US Patent:

60372621, Mar 14, 2000

Filed:

Jun 15, 1998

Appl. No.:

9/098032

Inventors:

Shouli Steve Hsia - San Jose CA
Jiunn-Yann Tsai - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21311

US Classification:

438700

Abstract:

A process is disclosed for forming vias and trenches in two separate dielectric layers, which may be separated by an etch stop, while avoiding the etch mask stress complicated resist masks, or high aspect ratio openings of the prior art. A first dielectric layer 10 is formed over an integrated circuit structure 2 on a semiconductor substrate, and a thin second dielectric layer 20 is formed over the first dielectric layer. A first resist mask, is formed over the second dielectric layer, and the first and second dielectric layers are etched through to form one or more vias 18, 28 extending through both the first and second dielectric layers. The first resist mask is then removed and a third dielectric layer 70, having different etch characteristics than the second dielectric layer, is deposited over the structure. This third dielectric layer, which may comprise the same material as the first dielectric layer, is applied to the structure as a low step coverage, nonconformal coating layer which preferably does not completely fill the one or more vias already formed in the first and second dielectric layers. A second resist mask is then applied over the third dielectric layer and the third dielectric layer is etched through to the underlying second dielectric layer to form the desired trench openings 78, with the second dielectric material acting as an etch stop, and also as an etch mask for removal of any of the third dielectric layer material which has deposited in the via(s) previously formed in the first and second dielectric layers.

US Patent:

60109521, Jan 4, 2000

Filed:

Jan 23, 1997

Appl. No.:

8/787992

Inventors:

Jiunn-Yann Tsai - San Jose CA
Zhihai Wang - Sunnyvale CA
Wen-Chin Yeh - Fremont CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2910

US Classification:

438528

Abstract:

An improved process is provided for amorphizing portions of a silicon substrate and a polysilicon gate electrode surface to be converted to metal silicide by subsequent reaction of the amorphized silicon with a metal layer applied over the silicon substrate and polysilicon gate electrode after the amorphizing step. The improvement comprises implanting the exposed surface of the silicon substrate and the surface of the polysilicon gate electrode with a beam of amorphizing ions at an angle of at least 15. degree. to a line perpendicular to the plane of the surface of the silicon substrate to thereby inhibit channeling of the implanted ions through the gate electrode to the underlying gate oxide and channel of the MOS structure. The implant angle of the beam of amorphizing ions is preferably at least 30. degree. , but should not exceed 60. degree.

US Patent:

58743421, Feb 23, 1999

Filed:

Jul 9, 1997

Appl. No.:

8/890222

Inventors:

Jiunn-Yann Tsai - San Jose CA
Zhihai Wang - Sunnyvale CA
Yen-Hui Joseph Ku - Cupertino CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21336

US Classification:

438301

Abstract:

A process which is capable of forming shallow source/drain regions in a silicon substrate and a doped gate electrode by implantation of cobalt silicide contacts of uniform thickness previously formed on the substrate followed by diffusion of the dopant into the substrate to form the desired source/drain regions, and into the polysilicon gate electrode to provide the desired conductivity is described. The process comprises: first depositing a layer of cobalt over a polysilicon gate electrode and areas of a silicon substrate where source/drain regions will be formed; then forming at least one capping layer over the cobalt layer; then annealing the structure at a first temperature to form cobalt silicide; then removing the capping layer, as well as the unreacted cobalt and any cobalt reaction products other than cobalt silicide; then annealing the structure again at a higher temperature than the first anneal to form high temperature cobalt silicide; then implanting the cobalt silicide with one or more dopants suitable for forming source/drain regions in the silicon substrate and for increasing the conductivity of the polysilicon gate electrode; and then heating the structure sufficiently to cause the implanted dopant or dopants in the cobalt silicide to diffuse into the substrate to form the desired source/drain regions and into the polysilicon gate electrode to increase the conductivity thereof.

US Patent:

61474096, Nov 14, 2000

Filed:

Jun 15, 1998

Appl. No.:

9/098019

Inventors:

Shouli Steve Hsia - San Jose CA
Fred Chen - Hsin-Chu, TW
Jiunn-Yann Tsai - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2348
H01L 2352
H01L 2940

US Classification:

257763

Abstract:

A composite metal line structure for an integrated circuit structure on a semiconductor substrate is disclosed which comprises: a low resistance metal core layer; a first thin protective layer of electrically conductive material on the upper surface of the metal core layer capable of protecting the metal core layer from reaction with tungsten; a layer of tungsten formed over the first protective layer to function as an etch stop layer for vias subsequently formed in an overlying dielectric layer; and a second thin protective layer of electrically conductive material over the tungsten layer and capable of functioning as an antireflective coating (ARC). When a dielectric layer is formed over the composite metal line structure, tungsten-filled vias can be formed in the dielectric layer which will extend down through the second thin protective layer to provide direct electrical contact between the tungsten-filled via and the tungsten layer of the composite metal line structure, thereby providing a low resistance contact between the tungsten-filled via and the composite metal line structure.

US Patent:

60202424, Feb 1, 2000

Filed:

Sep 4, 1997

Appl. No.:

8/926590

Inventors:

Jiunn-Yann Tsai - San Jose CA
Wen-Chin Yeh - Fremont CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21336

US Classification:

438279

Abstract:

A metal silicide blocking process for preventing formation of metal silicide on a first device and allowing formation of metal silicide on elements of a second device of an integrated circuit substrate is described. The process includes forming a gate electrode above the integrated circuit substrate, forming a first dielectric layer over the gate electrode and the substrate surface, forming a second dielectric layer above the first dielectric layer, etching anisotropically the second dielectric layer to form a second spacer portion adjacent to the first dielectric layer; masking the substrate surface of the first device to protect the first dielectric layer above the first device from being removed such that the substrate surface at the second device where the metal silicide is to be formed is exposed, etching the first dielectric layer to form a first spacer portion disposed between the gate electrode of the second device and the second spacer portion, the first spacer portion extends underneath the second spacer portion such that the first spacer portion is disposed between the second spacer portion and a portion of the substrate disposed beneath the second spacer portion, exposing the substrate surface of the first device, depositing a metal layer on the substrate surface and fusing metal ions from the metal layer with silicon ions from a plurality of device elements from the portion of the substrate surface where the metal silicide is to be formed to form metal silicide contact areas above the plurality of device elements.

US Patent:

58518908, Dec 22, 1998

Filed:

Aug 28, 1997

Appl. No.:

8/919394

Inventors:

Jiunn-Yann Tsai - San Jose CA
John Haywood - Santa Clara CA
Ming Yi Lee - Fremont CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21335

US Classification:

438303

Abstract:

A process for forming improved metal silicide contacts over the gate electrode and source/drain regions of MOS devices of an integrated circuit structure formed in a silicon substrate is described. The metal silicide contacts are formed by first forming a silicon oxide layer over exposed portions of the silicon substrate and over exposed surfaces of previously formed polysilicon gate electrodes. Silicon nitride sidewall spacers are then formed over the oxide on the sidewalls of the gate electrode by depositing a silicon nitride layer over the entire structure and then anisotropically etching the silicon nitride layer. Source/drain regions are then formed in the silicon substrate adjacent the nitride spacers and the structure is then contacted with an oxide etch to remove oxide from the upper surface of the gate electrode and the substrate surface over the source/drain regions. During the oxide etch step, notches, each having an aspect ratio of 1 or less, are formed in the exposed edges of the oxide respectively between the silicon nitride spacers and either the substrate or the gate electrode. A metal layer capable of reacting with the exposed silicon to form metal silicide contacts is then blanket deposited over the structure and into the notches.

US Patent:

60344016, Mar 7, 2000

Filed:

Feb 6, 1998

Appl. No.:

9/020029

Inventors:

Shouli Hsia - San Jose CA
Jiunn-Yann Tsai - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2994
H01L 2941
H01L 2352

US Classification:

257369

Abstract:

Disclosed is a process of electrically coupling the gate electrodes of an N-type transistor and a P-type transistor without causing substantial cross diffusion of P-type dopants into the N-type gate electrode and N-type dopants into the P-type gate electrode. This is possible because some or all annealing and diffusion steps are performed while the N-type and P-type gate electrodes are physically isolated from one another. Also disclosed is a Silicide as Diffusion Source process in which dopant atoms implanted in silicide regions diffuses out of the silicide regions and into the substrate to form source and drain diffusions. During this diffusion step adjacent N-type and P-type gate electrodes remain unconnected to prevent cross diffusion. Then, these two electrodes are electrically connected by a local interconnect. The local interconnection is a conductive path formed at about the level of the polysilicon (i. e.