Jiahui X Yuan from Fremont, CA, age 41

Us Patents

Superjunction Collectors For Transistors And Semiconductor Devices
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US Patent:

8546850, Oct 1, 2013
Filed:

Apr 8, 2010
Appl. No.:

13/148912
Inventors:

Jiahui Yuan - Atlanta GA, US
John D. Cressler - Smyrna GA, US
Assignee:

Georgia Gech Research Corporation - Atlanta GA
International Classification:

H01L 29/66
US Classification:

257197, 257565
Abstract:

Superjunction collectors for transistors are discussed in this application. According to one embodiment, a bipolar transistor having a superjunction collector structure can comprise a collector electrode, a base electrode, an emitter electrode, a collector-base space charge region, and a superjunction collector. The collector-base space charge region can be disposed in electrical communication between the collector electrode and the base electrode. The superjunction collector region can be disposed in the collector-base space charge region. The superjunction collector region can comprise a plurality of alternating horizontally disposed P-type and N-type layers. The layers can be horizontally disposed layers that are layered on top of each other. The P-type and N-type layers can be doped with different types of doping levels. Other aspects, embodiments, and features are also discussed and claimed.

Intelligent Shifting Of Read Pass Voltages For Non-Volatile Storage
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US Patent:

20120314499, Dec 13, 2012
Filed:

Jun 7, 2011
Appl. No.:

13/155323
Inventors:

Jiahui Yuan - Milpitas CA, US
Yingda Dong - San Jose CA, US
Charles Kwong - Redwood City CA, US
International Classification:

G11C 16/26
G11C 16/06
G11C 16/04
US Classification:

36518511, 36518518, 36518522
Abstract:

A first read pass voltage is determined and optimized for cycled memory. One or more starting read pass voltages are determined for one or more dies. The system dynamically calculates a current read pass voltage based on the number of program/erase erase cycles, the first read pass voltage and the respective starting read pass voltage. Data is read from one or more non-volatile storage elements using the calculated current read pass voltage.

Block Configuration For Memory Device With Separate Sub-Blocks
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US Patent:

20220415398, Dec 29, 2022
Filed:

Jun 28, 2021
Appl. No.:

17/360677
Inventors:

- Addison TX, US
Jiahui Yuan - Fremont CA, US
Deepanshu Dutta - Fremont CA, US
Assignee:

SanDisk Technologies LLC - Addison TX
International Classification:

G11C 16/08
G11C 16/04
Abstract:

A memory device is provided in which blocks of memory cells are divided into separate portions or sub-blocks with respective sets of word line switching transistors. The sub-blocks can be arranged on a substrate on opposite sides of a dividing line, where a separate set of bit lines is provided on each side of the dividing line. Each block has a row decoder which provides a common word line voltage signal to each sub-block of the block. However, each sub-block can have an independent set of word line switching transistors so that the common word line voltage signal can be passed or blocked independently for each sub-block. The blocks of memory cells can be provided on a first die which is inverted and bonded to a second die which includes the sets of word line switching transistors.

Multi-Level Program Pulse For Programming Single Level Memory Cells To Reduce Damage
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US Patent:

20220328112, Oct 13, 2022
Filed:

Apr 13, 2021
Appl. No.:

17/229705
Inventors:

- Addison TX, US
Jiahui Yuan - Fremont CA, US
Abhijith Prakash - Milpitas CA, US
Assignee:

SanDisk Technologies LLC - Addison TX
International Classification:

G11C 16/34
G11C 16/26
G11C 16/10
G11C 16/30
G11C 16/08
Abstract:

Apparatuses and techniques are described for reducing damage to memory cells during single bit per cell programming. An initial program pulse in a single bit per cell program operation has a lower, first program level followed by a higher, second program level. As a result of the lower, first program level, the electric field across the memory cells is reduced. The step up time from the first program level to the second program level can be reduced by concurrently stepping up pass voltages of the adjacent unselected word lines. If an additional program pulse is applied, the step up in the program pulse can be omitted. The magnitude of the first program level can be adjusted based on factors such as temperature, number of program-erase cycles, selected sub-block position and selected word line position.

Three-Dimensional Memory Device Including Multi-Bit Charge Storage Elements And Methods For Forming The Same
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US Patent:

20220254797, Aug 11, 2022
Filed:

Feb 8, 2021
Appl. No.:

17/169987
Inventors:

- ADDISON TX, US
Jiahui YUAN - Fremont CA, US
Senaka KANAKAMEDALA - San Jose CA, US
Raghuveer S. MAKALA - Campbell CA, US
Dana LEE - San Jose CA, US
International Classification:

H01L 27/11556
H01L 29/66
H01L 29/423
H01L 29/788
Abstract:

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from and is electrically isolated from the first memory material portion by at least one blocking dielectric material portion.

Three-Dimensional Memory Array Including Dual Work Function Floating Gates And Method Of Making The Same
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US Patent:

20220254798, Aug 11, 2022
Filed:

Jun 18, 2021
Appl. No.:

17/351720
Inventors:

- ADDISON TX, US
Yanli ZHANG - San Jose CA, US
Jiahui YUAN - Fremont CA, US
Raghuveer S. MAKALA - Campbell CA, US
Senaka KANAKAMEDALA - San Jose CA, US
International Classification:

H01L 27/11556
H01L 29/49
Abstract:

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures extending through the alternating stack, where each of the memory opening fill structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements is located at a level of a respective one of the electrically conductive layers between the respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from the first memory material portion. The second memory material portion has a different material composition from the first memory material portion.

Optimized Programming With A Single Bit Per Memory Cell And Multiple Bits Per Memory Cell
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US Patent:

20220223209, Jul 14, 2022
Filed:

Jan 14, 2021
Appl. No.:

17/149560
Inventors:

- Addison TX, US
Dongxiang Liao - Sunnyvale CA, US
Jiahui Yuan - Fremont CA, US
Assignee:

SanDisk Technologies LLC - Addison TX
International Classification:

G11C 16/10
G11C 16/04
G11C 16/08
G11C 16/34
G11C 11/56
Abstract:

Apparatuses and techniques are described for optimizing programming in a memory device in which memory cells can be programmed using single bit per cell programming and multiple bits per cell programming. In one aspect, a single bit per cell program operation is performed which reduces damage to the memory cells as well as reducing program time. The program operation can omit a pre-charge phase and a verify phase of an initial program loop of a program operation. Instead, a program phase is performed followed by a recovery phase. In one or more subsequent program loops of the single bit per cell program operation, as well as in each program loop of a multiple bit per cell program operation, the program loop includes a pre-charge phase, a program phase, a recovery phase and a verify phase.

Non-Volatile Memory With Reverse State Program
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US Patent:

20230091314, Mar 23, 2023
Filed:

Sep 22, 2021
Appl. No.:

17/481575
Inventors:

- San Jose CA, US
Liang Li - Shanghai, CN
Jiahui Yuan - Fremont CA, US
Assignee:

Western Digital Technologies, Inc. - San Jose CA
International Classification:

G11C 16/10
G11C 16/26
G11C 16/08
G11C 16/30
Abstract:

A memory system separately programs memory cells connected by a common word line to multiple sets of data states with the set of data states having higher threshold voltage data states being programmed before the set of data states having lower threshold voltage data states. The memory system also separately programs memory cells connected by an adjacent word line to the multiple sets of data states such that memory cells connected by the adjacent word line are programmed to higher data states after memory cells connected by the common word line are programmed to higher data states and prior to memory cells connected by the common word line are programmed to lower data states.