Jerry M Collings

US Patent:

6788233, Sep 7, 2004

Filed:

Aug 15, 2003

Appl. No.:

10/642420

Inventors:

Vincent Quiquempoix - Divonne-les-Bains, FR
Gabriele Bellini - Froideville, CH
Jerry Collings - Santa Clara CA

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

H03M 300

US Classification:

341143

Abstract:

A digital decimation filter with programmable frequency notches is disclosed. The digital decimation filter performs integration, differentiation, and scaling to produce a filtered output signal. The differentiation is preformed by a programmable counter. The filter has a control unit that controls the behavior of the filter. The control unit has registers to contain ther values of the frequency notches of the filter. The control unit activates the differentiator based on the value of the frequency notches in order to achieve filtration. The scaling unit uses a register, a bit shifter, and an adder to minimize complexity. The digital decimation filter provides high rejection with low complexity.

US Patent:

60548231, Apr 25, 2000

Filed:

May 19, 1998

Appl. No.:

9/081309

Inventors:

Jerry Collings - Santa Clara CA
Chuong Nguyen - San Jose CA
Joseph James Judkins - Cedar Park TX
Donald E. Alfano - Round Rock TX
Ali Tasdighi - San Jose CA
Quoi V. Huynh - San Jose CA
Sang T. Ngo - Cupertino CA

Assignee:

Telcom Semiconductor, Inc. - Mountain View CA

International Classification:

H01R 3946

US Classification:

318439

Abstract:

An apparatus for sensing the rotation of a brushless DC fan includes the fan and a sense/driver circuit and a capacitance. The sense/driver circuit is coupled to the fan to receive a sense input signal including a fluctuating electrical effect caused by fan commutation events. The sense/driver circuit processes the sense input signal to generate a sense output signal indicative of fan operation. The sense/driver circuit includes an integrated circuit. The integrated circuit includes a sense input pin, a ground return pin, a driver circuit, an integrated filter portion, a filter pin and a level detecting circuit. The capacitance is coupled to the filter pin to provide a filter with the integrated filter portion. The driver circuit includes a control terminal, a first current handling terminal coupled to the sense input pin and a second current handling terminal coupled to provide a ground return pat. The integrated filter portion includes a filter input coupled to at least one of the first and second current handling terminals of the driver circuit, and a filter output for providing a filter output signal to the level detecting circuit.

US Patent:

57342911, Mar 31, 1998

Filed:

Mar 11, 1996

Appl. No.:

8/613999

Inventors:

Ali Tasdighi - San Jose CA
Jerry M. Collings - Santa Clara CA

Assignee:

TelCom Semiconductor, Inc. - Mountain View CA

International Classification:

G05F 302

US Classification:

327537

Abstract:

An integrated circuit voltage converter containing a capacitive charge pump performing DC to DC conversion is disclosed which detects, either automatically or by an external signal, the onset of a low power consumption situation and switches to a low power consumption mode. In one embodiment, the low power consumption mode is accomplished by reducing the operating frequency of the charge pump. In another embodiment, the switching transistors used to switch the capacitors in the charge pump during a low power consumption mode are smaller than those transistors used to switch the capacitors during its normal operating mode. In another embodiment, the DC to DC converter switches back and forth between a high frequency (burst) mode and a low frequency (low power) mode at intervals. In another embodiment, a combination of the power reduction techniques is used. Various techniques for detecting when a low power consumption mode is appropriate are also described.

US Patent:

45715076, Feb 18, 1986

Filed:

May 12, 1982

Appl. No.:

6/377307

Inventors:

Jerry M. Collings - Santa Clara CA

Assignee:

Hybrid Systems Corporation - Billerica MA

International Classification:

H03K 500
H03K 5153

US Classification:

307350

Abstract:

A successive approximation analog-to-digital converter utilizes an improved high-gain current comparator having a zero input impedance characteristic in combination with an equal current digital-to-analog converter. The zero input impedance comparator permits the use of low power C-MOS switching circuitry by leading the output of the digital-to-analog converter to the zero impedance input of the comparator, thereby overcoming the problem of decreased switching speed associated with high capacitance C-MOS outputs. The zero impedance current comparator includes an improved current-to-voltage converter having an overdrive shunt circuit to reduce quiescent current and to permit higher value load resistors for better gain; and cascaded current cells to provide increased gain.