Jerald M Loy

US Patent:

51269201, Jun 30, 1992

Filed:

Sep 23, 1991

Appl. No.:

7/764439

Inventors:

Vahram S. Cardashian - Plymouth MN
Jerald M. Loy - Anoka MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

H05K 100

US Classification:

361398

Abstract:

A flexible chip interconnection includes a flexible film having interconnection lines formed on opposite sides thereof, with selected of the interconnection lines from one side connected by through-film conductors to interconnection lines on the other side. Insulating layers cover both sets of interconnection lines. Multi-chip circuits can be formed on the film with the interconnection lines directly connecting the chips.

US Patent:

48922455, Jan 9, 1990

Filed:

Nov 21, 1988

Appl. No.:

7/274431

Inventors:

Thomas J. Dunaway - St. Louis Park MN
Richard K. Speilberger - Maple Grove MN
Jerald M. Loy - Anoka MN
Lori A. Dicks - New Hope MN
Luverne O. Balgaard - Burnsville MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

B23K 3102
B23K 3704

US Classification:

2281802

Abstract:

Disclosed is a system and method for controlled compression furnace bonding of a semiconductor chip to conductive elements of a leadframe. The system comprises a holding member having a chip support surface for supporting a semiconductor chip and a positioning system for precisely positioning conductive elements of a leadframe with corresponding bonding locations on the semiconductor chip. A furnace heating system comprising a furnace is employed for heating and bonding the conductive elements to the chip bonding locations. The method invention comprises positioning a semiconductor chip comprising a plurality of bonding locations in a holding member with a chip support surface; providing performed bonding material for connecting conductive elements of a leadframe with the chip bonding locations; aligning the conductive elements of a leadframe with corresponding bonding locations on the semiconductor chip; moving the leadframe conductive elements toward the chip bonding locations so that the bonding material is aligned with the conductive elements in the chip bonding locations; furnace bond heating the bonding material to a point of reflow; and cooling the bonding material to complete the bonding process between the leadframe conductive elements and the corresponding chip bonding locations.

US Patent:

46493395, Mar 10, 1987

Filed:

Apr 25, 1984

Appl. No.:

6/603860

Inventors:

Robert H. Grangroth - Osseo MN
Jerald M. Loy - Anoka MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

G01R 3102
G01R 106

US Classification:

324158F

Abstract:

Disclosed is an interface for testing an integrated circuit device through a plurality of contacts on an exposed surface of the device. The interface comprises a flexible sheeting having first and second opposing surfaces. A plurality of contacts are disposed on the first surface of the sheet in a pattern designed to mate with a plurality of contacts on an integrated circuit device. A plurality of thin film conductors are patterned on the sheet, the conductors each being connected to a contact on the sheet and being adapted for connection to a circuit for testing the device. The interface comprises apparatus for preforming into a generally domed shape a portion of the sheet which includes a plurality of the contacts and apparatus for flexing the flexible sheet so that the contacts on both the sheet and the device may be brought into intimate contact.

US Patent:

49338102, Jun 12, 1990

Filed:

Apr 30, 1987

Appl. No.:

7/044861

Inventors:

Vahram S. Cardashian - Plymouth MN
Jerald M. Loy - Anoka MN
Frank S. Mills - Minneapolis MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

H05K 104

US Classification:

361398

Abstract:

A flexible film has electrical interconnections on each side. Through-film interconnects pass through openings in the film to connect the electrical interconnects on opposite sides of the film. Electrical contact patterns are formed on one side of the film to accomodate integrated circuit chips or other small electronic devices. Multi-chip circuits can be formed by connecting the chips to the pattern areas and connecting the patterns by way of the electrical interconnections on either side, or on both sides.

US Patent:

50103873, Apr 23, 1991

Filed:

Nov 21, 1988

Appl. No.:

7/274412

Inventors:

Thomas J. Dunaway - St Louis Park MN
Richard K. Spielberger - Maple Grove MN
Lori A. Dicks - New Hope MN
Jerald M. Loy - Anoka MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

H01L 2348
H01L 2354

US Classification:

357 70

Abstract:

Disclosed is a composition and method for providing conductive electronic component high strength bonding. The composition comprises an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead. The method invention comprises providing a leadframe comprising at least one of power, ground, and signal conductive elements; and preforming solder material onto one of the conductive elements, the solder bonding material having an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead.

US Patent:

51617293, Nov 10, 1992

Filed:

Jul 11, 1991

Appl. No.:

7/728622

Inventors:

Thomas J. Dunaway - St. Louis Park MN
Richard K. Spielberger - Maple Grove MN
Lori A. Dicks - New Hope MN
Jerald M. Loy - Anoka MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

H01L 2160

US Classification:

228179

Abstract:

Disclosed is a composition and method for providing conductive electronic component high strength bonding. The composition comprises an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead. The method invention comprises providing a leadframe comprising at lest one of power, ground, and signal conductive elements; and preforming solder material onto one of the conductive elements, the solder bonding material having an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead.

US Patent:

50666142, Nov 19, 1991

Filed:

Sep 28, 1990

Appl. No.:

7/589816

Inventors:

Thomas J. Dunaway - St. Louis Park MN
Richard K. Spielberger - Maple Grove MN
Lori A. Dicks - New Hope MN
Jerald M. Loy - Anoka MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

H01L 2160

US Classification:

437209

Abstract:

Disclosed is a composition and method for providing conductive electronic component high strength bonding. The composition comprises an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead. The method invention comprises providing a leadframe comprising at least one of power, ground, and signal conductive elements; and preforming solder material onto one of the conductive elements, the solder bonding material having an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead.

US Patent:

50993062, Mar 24, 1992

Filed:

Mar 26, 1991

Appl. No.:

7/677370

Inventors:

Thomas J. Dunaway - St. Louis Park MN
Richard K. Spielberger - Maple Grove MN
Jerald M. Loy - Anoka MN
Lori A. Dicks - New Hope MN
Francis J. Belcourt - Bloomington MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

H01L 2314
H01L 2348
H01L 2354

US Classification:

357 70

Abstract:

Disclosed is a stacked leadframe assembly for use with integrated circuit chips. The assembly comprises multiple leadframes arranged in stacked relation. Each leadframe comprises conductive elements and solder bumps for electrically and mechanically connecting selected conductive elements of the leadframes.