Jeffrey James Watt

US Patent:

6492710, Dec 10, 2002

Filed:

Jun 7, 2001

Appl. No.:

09/877905

Inventors:

Jeffrey T. Watt - Palo Alto CA

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H01L 2176

US Classification:

257544, 438220, 438356, 257547

Abstract:

A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposite conductivity type arranged between the well and the substrate. The integrated circuit may further include a pair of isolation wells extending along opposite lateral boundaries of the circuit well. The isolation wells and circuit well may be adapted such that a single continuous depletion region underlying the circuit well may be formed upon application of an isolation voltage between the substrate and the pair of isolation wells. The formation of such a depletion region may beneficially isolate the circuit well from the underlying substrate.

US Patent:

6537893, Mar 25, 2003

Filed:

Jul 11, 2002

Appl. No.:

10/194270

Inventors:

Jeffrey T. Watt - Palo Alto CA

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H01L 2176

US Classification:

438414, 438420

Abstract:

A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposite conductivity type arranged between the well and the substrate. The integrated circuit may further include a pair of isolation wells extending along opposite lateral boundaries of the circuit well. The isolation wells and circuit well may be adapted such that a single continuous depletion region underlying the circuit well may be formed upon application of an isolation voltage between the substrate and the pair of isolation wells. The formation of such a depletion region may beneficially isolate the circuit well from the underlying substrate.

US Patent:

6562675, May 13, 2003

Filed:

Aug 17, 2001

Appl. No.:

09/932159

Inventors:

Jeffrey T. Watt - Palo Alto CA

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H01L 218238

US Classification:

438217, 438276, 438289

Abstract:

A method is provided for processing a semiconductor topography. In particular, a method is provided for decreasing the threshold voltage magnitude of a first transistor being formed within the substrate while simultaneously increasing the threshold voltage magnitude of a second transistor being formed within the substrate. In some embodiments, a width of the first transistor may be larger than a width of the second transistor. In addition or alternatively, the method may include performing a first implantation corresponding to a threshold voltage magnitude above a desired value for the first transistor. The method may further include performing a second implantation to simultaneously lower the threshold voltage magnitude of the first transistor and raise a threshold voltage magnitude of the second transistor. In some embodiments, the method may include introducing dopants of a first conductivity type into a first transistor channel dopant region and a second transistor channel dopant region simultaneously.

US Patent:

6586296, Jul 1, 2003

Filed:

Apr 30, 2001

Appl. No.:

09/846666

Inventors:

Jeffrey T. Watt - Palo Alto CA

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H01L 218238

US Classification:

438224, 438419, 438532

Abstract:

A method is provided for processing a semiconductor topography. In particular, a method is provided for forming wells of opposite conductivity type using a single patterned layer. In addition, the method may include forming a silicon layer having first and second portions of opposite conductivity type. The formation of the silicon layer may include the use of the single patterned layer or an additional patterned layer. In addition, the method may include forming channel dopant regions within the wells of opposite conductivity type. The formation of such channel dopant regions may be incorporated into the method using the one or two patterned layers used for the formation of the wells and doped silicon layer. Such a method may include introducing impurities at varying energies and doses to compensate for the introduction of subsequent impurities. As such, the method may form a dual gate transistor pair, including n-channel and p-channel transistors.

US Patent:

6667224, Dec 23, 2003

Filed:

Aug 13, 2001

Appl. No.:

09/929829

Inventors:

Jeffrey T. Watt - Palo Alto CA
Kedar Patel - Fremont CA

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H01L 2176

US Classification:

438431

Abstract:

A method of making a semiconductor structure includes sealing a gate layer by wet oxidation. The gate layer is on a substrate containing isolation regions. Semiconductor devices prepared from the semiconductor structure exhibits reduced inverse narrow width effects.

US Patent:

6833330, Dec 21, 2004

Filed:

Dec 18, 2003

Appl. No.:

10/739674

Inventors:

Jeffrey T. Watt - Palo Alto CA
Kedar Patel - Fremont CA

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H01L 2131

US Classification:

438773, 438431

Abstract:

A method of making a semiconductor structure includes sealing a gate layer by wet oxidation. The gate layer is on a substrate containing isolation regions. Semiconductor devices prepared from the semiconductor structure exhibits reduced inverse narrow width effects.

US Patent:

6881634, Apr 19, 2005

Filed:

Aug 30, 2002

Appl. No.:

10/232586

Inventors:

Jeffrey T. Watt - Palo Alto CA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H01L021/336
H01L021/8238

US Classification:

438289, 438217, 438291, 438218, 438228

Abstract:

In one embodiment, a buried-channel transistor is fabricated by masking a portion of an active region adjacent to a trench and implanting a dopant in an exposed portion of the active region to adjust a threshold voltage of the transistor. By masking a portion of the active region, the dopant is substantially prevented from getting in a region near an edge of the trench. Among other advantages, this results in reduced leakage current.

US Patent:

6921948, Jul 26, 2005

Filed:

Mar 20, 2003

Appl. No.:

10/393032

Inventors:

Jeffrey T. Watt - Palo Alto CA, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H01L029/76
H01L029/94
H01L031/062
H01L031/113
H01L031/119

US Classification:

257369, 257391

Abstract:

A method is provided for processing a semiconductor topography. In particular, a method is provided for decreasing the threshold voltage magnitude of a first transistor being formed within the substrate while simultaneously increasing the threshold voltage magnitude of a second transistor being formed within the substrate. In some embodiments, a width of the first transistor may be larger than a width of the second transistor. In addition or alternatively, the method may include performing a first implantation corresponding to a threshold voltage magnitude above a desired value for the first transistor. The method may further include performing a second implantation to simultaneously lower the threshold voltage magnitude of the first transistor and raise a threshold voltage magnitude of the second transistor. In some embodiments, the method may include introducing dopants of a first conductivity type into a first transistor channel dopant region and a second transistor channel dopant region simultaneously.