Javed S Barkatullah from 13400 Briarwick Dr #301, Austin, TX 78729, age 62

Name / Title

Company / Classification

Phones & Addresses

Javed S Barkatullah
Director, Principal

Barkatech Consulting, LLC
Information Technology and Services · Business Consulting Services

4804 NW Bethany Blvd STE I-2, #162, Portland, OR 97229
14197 NW Stonebridge Dr, Portland, OR 97229

Javed Barkatullah
Principal

Global Mems Holdings, LLC
Holding Company

1234 SW 18 Ave, Portland, OR 97205

Javed Barkatullah
Principal

Gobenow, Inc
Nonclassifiable Establishments

14197 NW Stonebridge Dr, Portland, OR 97229

Resumes

Solutions Architect

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Location:

Austin, TX

Industry:

Computer Hardware

Work:

Everspin Technologies May 2015 - Apr 2017
Distinguished Member of Technical Staff
Cadence Design Systems May 2015 - Apr 2017
Solutions Architect
Everspin Technologies Mar 2015 - May 2015
Consultant
Barkatech Consulting Jan 2010 - May 2015
Founder and Chief Engineer
Gobenow Apr 2011 - Dec 2013
Chief Executive Officer and Co-Founder

Education:

Willamette University - Atkinson Graduate School of Management 2010 - 2012
MBA, Sustainable Enterprise and Entrepreneurship University of Iowa 1987 - 1992
MS, Ph.D, Electrical & Computer Engineering Bangladesh University of Engineering and Technology 1981 - 1985
BS, Electrical & Electronics Engineering

Skills:

Microprocessors
Verilog
Processors
Asic
Integrated Circuit Design
Circuit Design
Project Management
Mixed Signal
Simulations
Soc
Semiconductor Industry
New Business Development
Ic
Clocking
Semiconductors
Application Specific Integrated Circuits
Start Ups
New Technology Development
High Speed Design
Debugging
Rtl Design
Hardware Architecture
High Speed Circuit Design
Microprocessor Clocking
Mixed Signal Circuit Design
Stereoscopic and Autostereoscopic Video System
Software Design and Development
Systemverilog
16Nm Design
Vlsi
System on A Chip
2D To 3D Conversion
Functional Verification
Open Verification Methodology
Eda
Algorithms
Bitcoin Mining
Cryptography
Finfet
Tcl
Physical Design
Cross Functional Team Leadership
Microarchitecture

Interests:

Human Rights
Science and Technology
Environment
Disaster and Humanitarian Relief

Javed Barkatullah

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Us Patents

Clock Distribution System For Selectively Enabling Clock Signals To Portions Of A Pipelined Circuit
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US Patent:

6611920, Aug 26, 2003
Filed:

Jan 21, 2000
Appl. No.:

09/489153
Inventors:

Thomas D. Fletcher - Portland OR
Javed S. Barkatullah - Portland OR
Douglas Carmean - Beaverton OR
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 132
US Classification:

713322, 713320, 713324
Abstract:

A hierarchical power control system for an integrated circuit may be integrated into a clocking system that includes a global clock generator, a clock distribution network in communication with the global clock generator and a plurality of functional unit blocks each in communication with the global clock generator. The hierarchical power control system may include a first power controller provided in a communication path between the global clock generator and the clock distribution network, and a plurality of second power controllers, one provided in each communication path between the clock distribution network and a functional unit block.

Digital Clock Skew Detection And Phase Alignment
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US Patent:

6622255, Sep 16, 2003
Filed:

Sep 13, 2000
Appl. No.:

09/660808
Inventors:

Nasser A. Kurd - Hillsboro OR
Javed Barkatullah - Portland OR
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 112
US Classification:

713503, 713401
Abstract:

A skew measure circuit, an exclusion circuit, and an up/down counter are connected to form a skew detection circuit. The skew measure circuit asserts a first output signal if a first input clock leads a second input clock, and asserts a second output signal if the second clock leads the first clock. The exclusion circuit provides first and second digital pulse signals that represent the outputs of the skew measure circuit. The exclusion circuit also prevents the states of these pulse signals from changing, so long as the skew measure circuit is experiencing metastability. The up/down counters count is incremented in response to the first pulse signal and decremented in response to the other pulse signal.

Generating A 2-Phase Clock Using A Non-50% Divider Circuit
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US Patent:

6629255, Sep 30, 2003
Filed:

May 22, 2000
Appl. No.:

09/576943
Inventors:

Javed S. Barkatullah - Portland OR
Thomas D. Fletcher - Portland OR
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 104
US Classification:

713500, 713401, 713503, 327100
Abstract:

A logic circuit is disclosed having a digital divider that is capable of generating an intermediate signal in response to an input digital clock signal having a 50% duty cycle, where the intermediate signal has a non-50% duty cycle. First and second output signals are generated by a digital delay circuit in response to the intermediate signal. In the digital delay circuit, the first output signal is delayed by an odd number of substantially identical inverter delays, while the second output signal is delayed by an even number of inverter delays. Such a circuit helps reduce and perhaps minimize the sensitivity of the relative phase difference between the output signals to variations in temperature, supply voltage, and fabrication process parameters. When generated locally, this 2-phase clock does not require the distribution of two clock signals throughout the integrated circuit die or printed wiring board, but rather just one, thereby simplifying both the layout of the circuit as well as the control of clock accuracy in the system.

Automated Clock Alignment For Testing Processors In A Bypass Mode
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US Patent:

6704892, Mar 9, 2004
Filed:

May 31, 2000
Appl. No.:

09/583268
Inventors:

Nasser A. Kurd - Hillsboro OR
Javed S. Barkatullah - Portland OR
Tim Frodsham - Portland OR
David J. OBrien - Portland OR
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G01R 3128
US Classification:

714724, 327163, 709400
Abstract:

In a bypass mode, a tester may bypass the core and input/output phase locked loops (PLLs) utilized by a processor to develop internal clock signals. External, tester-generated, phase shifted clock signals may be used to generate aligned high frequency signals to replace those generated by the phase locked loops. A plurality of phase shifted, tester generated clock signals may be subjected to an exclusive OR operation for generating input/output and core clock replacement signals. The clock signals received from the tester may also be aligned. Thus, a variety of skews may be compensated before entering the bypass mode. In some embodiments of the present invention, the core and I/O PLL clocks are used to establish alignment in a set-up phase and in other embodiments, the core and I/O PLL need not be utilized at all to generate appropriate internal clock signals from an external tester.

Method And Apparatus For Correcting A Clock Duty Cycle In A Clock Distribution Network
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US Patent:

6750689, Jun 15, 2004
Filed:

Mar 29, 2001
Appl. No.:

09/823098
Inventors:

Thomas D. Fletcher - Portland OR
Javed S. Barkatullah - Portland OR
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03K 3017
US Classification:

327175, 327155, 327291
Abstract:

A clock duty cycle correction circuit. The duty cycle correction circuit is located at a receiver in a clock distribution network to correct a duty cycle of a distributed clock signal.

Method And Apparatus For Detecting On-Die Voltage Variations
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US Patent:

6882238, Apr 19, 2005
Filed:

Mar 21, 2003
Appl. No.:

10/394938
Inventors:

Nasser A. Kurd - Portland OR, US
Javed S. Barkatullah - Portland OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03B001/00
US Classification:

331186, 331185, 331 74
Abstract:

On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Adaptive Frequency Clock Signal
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US Patent:

6922111, Jul 26, 2005
Filed:

Dec 20, 2002
Appl. No.:

10/326695
Inventors:

Nasser A. Kurd - Portland OR, US
Javed S. Barkatullah - Portland OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G01N027/00
US Classification:

331 48, 331 65
Abstract:

According to some embodiments, a clock signal having an adaptive frequency is provided.

Clock Signal Generation And Distribution Via Ring Oscillators
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US Patent:

6922112, Jul 26, 2005
Filed:

Jun 25, 2002
Appl. No.:

10/179861
Inventors:

Nasser A. Kurd - Hillsboro OR, US
Javed S. Barkatullah - Portland OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03B027/00
US Classification:

331 57, 327295
Abstract:

According to some embodiments, a plurality of ring oscillators are associated with a generation and/or distribution of a clock signal.