James G Schleicher

US Patent:

6362646, Mar 26, 2002

Filed:

Jan 30, 1998

Appl. No.:

09/016544

Inventors:

James Schleicher - Sunnyvale CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 40, 326 41, 326 47

Abstract:

The invention relates to a method and an apparatus for reducing memory resources in an integrated circuit. Typically, the integrated circuit chip is a complex programmable logic device architecture (CPLD). The integrated circuit includes a plurality of interconnection lines as well as a first type function block capable of being programmed to operate in a first plurality of modes. The first type function block includes a first plurality of function block Input/Output (I/O) lines. The integrated circuitry also includes a second type function block capable of being programmed to operate in a second plurality of modes. The second type function block includes a second plurality of function block Input/Output (I/O) lines. The integrated circuit includes a shared programmable interface array device operatively connected to the first and second type function blocks. The shared programmable interface array device programmably interconnects the interconnection lines to the function block I/O lines of the first and second type function blocks.

US Patent:

6366120, Apr 2, 2002

Filed:

Mar 2, 2000

Appl. No.:

09/517146

Inventors:

James Schleicher - Santa Clara CA
James Park - San Jose CA
Bruce Pedersen - San Jose CA
Tony Ngai - Campbell CA
Wei-Jen Huang - Burlingame CA
Victor Maruri - Mountain View CA
Rakesh Patel - Cupertino CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 190177

US Classification:

326 41, 326 40, 326 39

Abstract:

A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

US Patent:

6407576, Jun 18, 2002

Filed:

Mar 2, 2000

Appl. No.:

09/516921

Inventors:

Tony Ngai - Campbell CA
Bruce Pedersen - San Jose CA
James Schleicher - Santa Clara CA
Wei-Jen Huang - Burlingame CA
Michael Hutton - Palo Alto CA
Victor Maruri - Mountain View CA
Rakesh Patel - Cupertino CA
Peter J. Kazarian - Cupertino CA
Andrew Leaver - Palo Alto CA
David W. Mendel - Sunnyvale CA
Jim Park - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 2500

US Classification:

326 41, 326 39, 326 47

Abstract:

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e. g. , interconnection conductors, signal buffers/drivers, programmable connectors, etc. ) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e. g. , with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e. g. , clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

US Patent:

6480028, Nov 12, 2002

Filed:

Feb 1, 2002

Appl. No.:

10/062741

Inventors:

David E. Jefferson - San Jose CA
Cameron McClintock - Mountain View CA
James Schleicher - Santa Clara CA
Andy L. Lee - San Jose CA
Manuel Mejia - San Jose CA
Bruce B. Pederson - San Jose CA
Christopher F. Lane - Campbell CA
Richard G. Cliff - Milpitas CA
Srinivas T. Reddy - Fremont CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 40

Abstract:

A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

US Patent:

6525564, Feb 25, 2003

Filed:

Dec 14, 2001

Appl. No.:

10/017199

Inventors:

James Schleicher - Santa Clara CA
James Park - San Jose CA
Bruce Pedersen - San Jose CA
Tony Ngai - Campbell CA
Wei-Jen Huang - Burlingame CA
Victor Maruri - Mountain View CA
Rakesh Patel - Cupertino CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 190177

US Classification:

326 41, 326 40, 326 39

Abstract:

A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

US Patent:

6614261, Sep 2, 2003

Filed:

Jan 14, 2002

Appl. No.:

10/047618

Inventors:

Tony Ngai - Campbell CA 95008
Bruce Pedersen - San Jose CA 95136
James Schleicher - Santa Clara CA 95050
Wei-Jen Huang - Burlingame CA 94010
Victor Maruri - Mountain View CA 94041
Rakesh Patel - Cupertino CA 95014

International Classification:

H03K 19177

US Classification:

326 41, 326 39, 326101

Abstract:

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e. g. , interconnection conductors, signal buffers/drivers, programmable connectors, etc. ) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e. g. , with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e. g. , clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

US Patent:

6727727, Apr 27, 2004

Filed:

Nov 18, 2002

Appl. No.:

10/299572

Inventors:

James Schleicher - Santa Clara CA
James Park - San Jose CA
Bruce Pedersen - San Jose CA
Tony Ngai - Campbell CA
Wei-Jen Huang - Burlingame CA
Victor Maruri - Mountain View CA
Rakesh Patel - Cupertino CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 190177

US Classification:

326 41, 326 40, 326 39

Abstract:

A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

US Patent:

6747480, Jun 8, 2004

Filed:

Jul 12, 2002

Appl. No.:

10/195209

Inventors:

Sinan Kaptanoglu - Belmont CA
Michael D. Hutton - Mountain View CA
James Schleicher - Santa Clara CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 47

Abstract:

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. The regions of logic may include logic subregions that each have a look-up table. Interconnection resources (e. g. , inter-region and intra-region interconnection conductors, signal buffers and drivers, programmable connectors, etc. ) are provided on the device for making programmable interconnections between the look-up tables. Programmable bidirectional cascade circuitry that is distinct from the interconnections may be used to make connections directly from the output of one look-up table to another without using the interconnection resources. The programmable cascade circuitry may be programmed so that multiple look-up tables are interconnected to form sequential cascade chains or cascade trees.