James Wynne Mobley

US Patent:

6356100, Mar 12, 2002

Filed:

Jan 19, 2001

Appl. No.:

09/766181

Inventors:

James Bryce Mobley - Austin TX

Assignee:

Dell Products L.P. - Round Rock TX

International Classification:

H03K 1718

US Classification:

326 26, 326 28, 326 86, 326 93

Abstract:

A technique for reducing such ground bounce using phased outputs and package de-skewing for source synchronous buses is described. In one embodiment, the output buffers of an integrated circuit (âICâ) are phased so that half of the buffer outputs are driven first and the remaining half are driven a slight time delay later. The outputs are then de-skewed by package routing so that the earlier signals reach the package pins at the same time as the later signals. This deskewing is accomplished by serpentining and length-matching the bank of non-delayed outputs so that these trace-induced delays match an optimized fixed clock delay used to delay the bank of delayed outputs, the traces of which are length-matched and routed as short as possible.

US Patent:

6396301, May 28, 2002

Filed:

Jan 19, 2001

Appl. No.:

09/766203

Inventors:

James Bryce Mobley - Austin TX

Assignee:

Dell Products L.P. - Round Rock TX

International Classification:

H03K 1716

US Classification:

326 31, 326 27, 327 74

Abstract:

A methodology for predicting incidents of ground bounce and using this information for reducing data error caused thereby is described. In one embodiment, data to be clocked into a plurality of output buffers from a first register is read before it goes to the buffers and a determination is made as to what number of bits B will change state, i. e. , from a zero to a one or a one to a zero. B is then compared to a predetermined threshold T. If B is greater than T, a wait state or some other indication is issued when the bits are clocked into the I/O buffers.

US Patent:

6806729, Oct 19, 2004

Filed:

Jan 19, 2001

Appl. No.:

09/766204

Inventors:

James Bryce Mobley - Austin TX

Assignee:

Dell Products L.P. - Round Rock TX

International Classification:

H03K 19003

US Classification:

326 33, 326 27

Abstract:

A circuit for detecting ground bounce and for using the detection information to reduce data error resulting therefrom is described. In one embodiment an on-chip ground bounce detector circuit detects large ground bounce events caused by the simultaneous switching of I/O buffers of the chip and notifies an on-chip logic circuit of the event The on-chip logic circuit can be implemented to take a variety of actions upon receipt of notification from the detection circuit that a ground bounce has been detected.

US Patent:

6906531, Jun 14, 2005

Filed:

Oct 11, 2002

Appl. No.:

10/269355

Inventors:

James B. Mobley - Austin TX, US

Assignee:

Dell Products L.P. - Round Rock TX

International Classification:

G01R027/26

US Classification:

324672, 324613

Abstract:

An adaptive reference voltage method and system analyzes a received bus signal to evaluate voltage swing characteristics and adjusts the reference voltage for reading the signal to a level that compensates for variations in margins between high and low signal switching values such as are introduced by noise. A bus input signal analyzer circuit incorporated in an integrated circuit analyzes the bus signal received at the integrated circuit to adjust the reference voltage used by the integrated circuit. In one embodiment, the bus input signal analyzer circuit applies a feedback loop to adapt the reference voltage by setting high and low input values to a reference voltage generation circuit with the reference voltage centered between the high and low values, such as results from a resistor divider network.

US Patent:

7405634, Jul 29, 2008

Filed:

Jan 30, 2004

Appl. No.:

10/769060

Inventors:

James B. Mobley - Austin TX, US
Robert Washburn - Austin TX, US

Assignee:

Dell Products L.P. - Round Rock TX

International Classification:

H01P 3/08

US Classification:

333 1, 333 4, 333246

Abstract:

An improved method and apparatus for altering the effective electrical length of trace on a circuit board. In the present invention small tabs of etch are routed perpendicular to the trace in the unused areas between adjacent traces. In an embodiment of the invention, a method of tuning the delay characteristics of a transmission line is implemented by inserting compensation tabs into the unused area between the segments of adjacent straight traces or a serpentine run. Utilizing the method and apparatus of the present invention, it is possible to achieve significantly greater electrical length for an electrical trace without introducing coupling problems or utilizing large amounts of space on a circuit board.

US Patent:

20050201489, Sep 15, 2005

Filed:

May 2, 2005

Appl. No.:

11/119577

Inventors:

James Mobley - Austin TX, US

International Classification:

H04L025/06

US Classification:

375317000, 324672000, 324705000

Abstract:

An adaptive reference voltage method and system analyzes a received bus signal to evaluate voltage swing characteristics and adjusts the reference voltage for reading the signal to a level that compensates for variations in margins between high and low signal switching values such as are introduced by noise. A bus input signal analyzer circuit incorporated in an integrated circuit analyzes the bus signal received at the integrated circuit to adjust the reference voltage used by the integrated circuit. In one embodiment, the bus input signal analyzer circuit applies a feedback loop to adapt the reference voltage by setting high and low input values to a reference voltage generation circuit with the reference voltage centered between the high and low values, such as results from a resistor divider network.

US Patent:

55046894, Apr 2, 1996

Filed:

Dec 16, 1993

Appl. No.:

8/168629

Inventors:

Gregory R. Fiebrich - Austin TX
James B. Mobley - Austin TX

Assignee:

Dell USA, L.P. - Austin TX

International Classification:

G01R 3102

US Classification:

364481

Abstract:

Disclosed are an apparatus and method preferably for testing personal computer (PC) bus transmission line characteristics. The apparatus comprises: (1) a plurality of transmission line segments having different physical dimensions, each of the plurality of segments having a different electrical effect on signals transmitted thereon and (2) a switching circuit capable of coupling successive ones of the plurality of segments to an external conductor, an electrical characteristic of the external conductor affected by the coupling of the successive ones of the plurality of segments thereto, the apparatus permitting signals to pass through the external conductor and a selected one of the plurality of segments via the switching circuit. The apparatus allows a determination of a susceptibility of the external conductor to changes in transmission line electrical characteristics brought about by various possible combinations of peripheral expansion bus cards.