James B Crossland

US Patent:

6917999, Jul 12, 2005

Filed:

Jun 29, 2001

Appl. No.:

09/895692

Inventors:

Mohan J. Kumar - Aloha OR, US
Shivnandan D. Kaushik - Portland OR, US
James B. Crossland - Banks OR, US
Linda J. Rankin - Portland OR, US
David J. O'Shea - Costa Mesa CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F013/00

US Classification:

710302, 710300, 710301

Abstract:

One aspect of the invention relates to creation of a container object being part of software that is stored in platform readable medium and executed by a processor within a platform. The container comprises (i) a hardware identification object to identify to an operating system of the platform that a type of device represented by the container object is a node and (ii) a plurality of component objects to identify constituent components of the node. Another aspect of the invention is the distribution of BIOS to handle initiation of components of a substrate in response to hot-plug addition of that substrate.

US Patent:

6920581, Jul 19, 2005

Filed:

Jan 2, 2002

Appl. No.:

10/038323

Inventors:

Bryant E. Bigbee - Scottsdale AZ, US
Shivnandan Kaushik - Portland OR, US
James B. Crossland - Banks OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F011/00

US Classification:

714 10, 717124

Abstract:

A method and apparatus for functional redundancy check mode recovery is disclosed. A method in accordance with one embodiment includes detecting an event associated with a device within a data processing system, initiating a platform-independent device removal sequence for the device in response to detecting the event, virtually ejecting the device from the data processing system in response to initiating the platform-independent device removal sequence, and servicing the event associated with the device in response to virtually ejecting the device from the data processing system.

US Patent:

7000102, Feb 14, 2006

Filed:

Jun 29, 2001

Appl. No.:

09/895580

Inventors:

Mohan J. Kumar - Aloha OR, US
Shivnandan D. Kaushik - Portland OR, US
James B. Crossland - Banks OR, US
Linda J. Rankin - Portland OR, US
David J. O'Shea - Costa Mesa CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/445
G06F 1/26

US Classification:

713 2, 713323

Abstract:

One aspect of the invention relates to a method for supporting hibernation despite the presence of hot-plugged nodes and non-deterministic boot operations. The method comprises invoking a management interrupt in response to a Hibernate request. The management interrupt is used to obtain and store platform configuration information into a non-volatile storage location. The platform configuration information includes data to indicate whether a next boot sequence for a platform occurs as a deterministic boot sequence or a non-deterministic boot sequence as well as a boot node identifier and a listing of an order in which processors of the platform are initialized.

US Patent:

7127561, Oct 24, 2006

Filed:

Dec 31, 2001

Appl. No.:

10/039656

Inventors:

David L. Hill - Cornelius OR, US
Deborah T. Marr - Portland OR, US
Dion Rodgers - Hillsboro OR, US
Shiv Kaushik - Portland OR, US
James B. Crossland - Banks OR, US
David A. Koufaty - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/08

US Classification:

711145, 711118, 711122, 711123, 711141, 711144, 711173, 711147, 711148, 711170, 718100, 718102, 718107

Abstract:

Coherency techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes a cache, execution logic to execute an instruction having an operand indicating a monitor address and a bus controller. In one embodiment, the bus controller is to assert a preventative signal in response to receiving a memory access attempting to gain sufficient ownership of a cache line associated with said monitor address to allow modification of said cache line without generation of another transaction indicative of the modification. In another embodiment, the bus controller is to generate a bus cycle in response to the instruction to eliminate any ownership of the cache line by another processor that would allow a modification of the cache line without generation of another memory access indicative of the modification.

US Patent:

7191349, Mar 13, 2007

Filed:

Dec 26, 2002

Appl. No.:

10/330622

Inventors:

Shivnandan D. Kaushik - Portland OR, US
John W. Horigan - Mountain View CA, US
Alon Naveh - Ramat Hasharon, IL
James B. Crossland - Banks OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/00
G06F 1/30
G06F 1/32

US Classification:

713323, 713300, 713320, 713322, 713324

Abstract:

A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.

US Patent:

7213093, May 1, 2007

Filed:

Jun 27, 2003

Appl. No.:

10/608708

Inventors:

Per Hammarlund - Hillsboro OR, US
James B. Crossland - Banks OR, US
Anil Aggarwal - Portland OR, US
Shivnandan D. Kaushik - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/14
G06F 9/46
G06F 13/00

US Classification:

710200, 718102, 718104, 719315

Abstract:

A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.

US Patent:

7328293, Feb 5, 2008

Filed:

Mar 9, 2007

Appl. No.:

11/716377

Inventors:

Per Hammarlund - Hillsboro OR, US
James B. Crossland - Banks OR, US
Anil Aggarwal - Portland OR, US
Shivnandan D. Kaushik - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00
G06F 9/46
G06F 9/50

US Classification:

710200, 718102, 718104, 719315

Abstract:

A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.

US Patent:

7546487, Jun 9, 2009

Filed:

Sep 15, 2005

Appl. No.:

11/227831

Inventors:

Suresh Marisetty - Fremont CA, US
Andrew J. Fish - Olympia WA, US
Koichi Yamada - Los Gatos CA, US
Scott D. Brenden - Bothell WA, US
James B. Crossland - Banks OR, US
Shivnandan Kaushik - Portland OR, US
Mohan J. Kumar - Aloha OR, US
Jose A. Vargas - Rescue CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00
G06F 11/07

US Classification:

714 27, 714 10, 714 37

Abstract:

Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to access firmware error-handling services. Such services enable the OS to access error data concerning platform hardware errors that may not be directed accessed via a platform processor or through other conventional approaches. Techniques are also disclosed for intercepting the processing of hardware error events and directing control to firmware error-handling services prior to attempting to service the error using OS-based services. The firmware services may correct hardware errors and/or log error data that may be later accessed by the OS or provided to a remote management server using an out-of-band communication channel. In accordance with another aspect, the firmware intercept and services may be performed in a manner that is transparent to the OS.