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Igor Peidous

from Lake Saint Louis, MO

Igor Peidous Phones & Addresses

  • Lake Saint Louis, MO
  • 1732 Washington Landing Dr, Eaton, OH 45320
  • 21 Springwood Manor Dr, Albany, NY 12211 • 518-462-0702
  • 14600 Marsh Ln, Addison, TX 75001 • 972-247-5131
  • 14700 Marsh Ln, Addison, TX 75001 • 972-247-5131 • 972-620-8426
  • 14700 Marsh Ln #1221, Addison, TX 75001 • 972-247-5131
  • 732 Huntington Dr, Fishkill, NY 12524
  • 71 Saybridge Manor Pkwy, Lake Saint Louis, MO 63367

Education

  • Degree:
    Associate degree or higher

Us Patents

  • Methods For Fabrication Of A Stressed Mos Device

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  • US Patent:
    7326601, Feb 5, 2008
  • Filed:
    Sep 26, 2005
  • Appl. No.:
    11/235791
  • Inventors:
    Frank Wirbeleit - Wappingers Falls NY, US
    Linda R. Black - Wappingers Falls NY, US
    Igor Peidous - Fishkill NY, US
  • Assignee:
    Advanced Micro Devices, Inc. - Austin TX
  • International Classification:
    H01L 21/84
  • US Classification:
    438151, 438275, 257E21561
  • Abstract:
    Methods for fabricating a stressed MOS device is provided. One method comprises the steps of providing a monocrystalline semiconductor substrate having a surface and a channel abutting the surface. A gate electrode having a first edge and a second edge is formed overlying the monocrystalline semiconductor substrate. The substrate is anisotropically etched to form a first recess aligned with the first edge and a second recess aligned with the second edge. The substrate is further isotropically etched to form a third recess in the substrate extending beneath the channel. The third recess is filled with an expanding material to exert an upward force on the channel and the first and second recesses are filled with a contact material. Conductivity determining ions are implanted into the contact material to form a source region and a drain region aligned with the first and second edges, respectively.
  • Methods For Fabricating A Cmos Device Including Silicide Contacts

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  • US Patent:
    7348233, Mar 25, 2008
  • Filed:
    Aug 19, 2005
  • Appl. No.:
    11/207265
  • Inventors:
    Martin Gerhardt - Dresden, DE
    Igor Peidous - Fishkill NY, US
  • Assignee:
    Advanced Micro Devices, Inc. - Austin TX
  • International Classification:
    H01L 21/8238
  • US Classification:
    438199, 438303, 438306, 438682, 257384, 257E21634, 257E21619
  • Abstract:
    Methods are provided for fabricating a CMOS device having a silicon substrate including a first N-type region and a second P-type region. The method includes the steps of forming a first gate electrode overlying the first N-type region and a second gate electrode overlying the second P-type region. P-type source and drain regions are ion implanted into the first N-type region, and N-type source and drain regions are ion implanted into the second P-type region. First silicide regions, spaced apart from the first gate electrode by a first distance, are formed contacting the P-type source and drain regions, and second silicide regions, spaced apart from the second gate electrode by a second distance less than the first distance, are formed contacting the N-type source and drain regions.
  • Stressed Mos Device And Method For Its Fabrication

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  • US Patent:
    7410859, Aug 12, 2008
  • Filed:
    Nov 7, 2005
  • Appl. No.:
    11/269241
  • Inventors:
    Igor Peidous - Fishkill NY, US
    Linda R. Black - Wappingers Falls NY, US
    Frank Wirbeleit - Dresden, DE
  • Assignee:
    Advanced Micro Devices, Inc. - Austin TX
  • International Classification:
    H01L 21/8238
    H01L 21/336
  • US Classification:
    438231, 438199, 438301, 257E21561
  • Abstract:
    A stressed MOS device and a method for its fabrication are provided. The MOS device comprises a substrate having a surface, the substrate comprising a monocrystalline semiconductor material having a first lattice constant. A channel region is formed of the monocrystalline silicon material adjacent the surface. A stress inducing monocrystalline semiconductor material having a second lattice constant greater than the first lattice constant is grown under the channel region to exert a horizontal tensile stress on the channel region.
  • Methods For Fabricating Semiconductor Substrates With Silicon Regions Having Differential Crystallographic Orientations

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  • US Patent:
    7432174, Oct 7, 2008
  • Filed:
    Mar 30, 2007
  • Appl. No.:
    11/693890
  • Inventors:
    Igor Peidous - Fishkill NY, US
  • Assignee:
    Advanced Micro Devices, Inc. - Austin TX
  • International Classification:
    H01L 21/46
  • US Classification:
    438459, 438458, 438457, 438455, 438E21564
  • Abstract:
    A method is provided for fabricating a differential semiconductor substrate. A first structure is provided which comprises a first semiconductor substrate including a first semiconductor region, and a first oxide layer overlying a surface of the first semiconductor substrate. The first semiconductor substrate has a first crystallographic orientation. A second structure is provided which includes a second semiconductor substrate comprising a first layer and a second layer, and a second oxide layer which overlies a surface of the first layer. The second semiconductor substrate has a second crystallographic orientation different than the first crystallographic orientation. The first layer includes a second semiconductor region. The first layer and the second oxide layer are removed from the second structure, and assembled to the first semiconductor substrate to form a composite structure. A bonded composite structure is then formed by exposing the composite structure to a temperature adequate to cause bonding of the first oxide layer and the second oxide layer.
  • Stressed Mos Device And Methods For Its Fabrication

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  • US Patent:
    7456058, Nov 25, 2008
  • Filed:
    Sep 21, 2005
  • Appl. No.:
    11/231405
  • Inventors:
    Igor Peidous - Fishkill NY, US
    Linda R. Black - Wappingers Falls NY, US
    Huicai Zhong - Wappingers Falls NY, US
  • Assignee:
    Advanced Micro Devices, Inc. - Austin TX
  • International Classification:
    H01L 21/338
  • US Classification:
    438182, 438574, 438585
  • Abstract:
    Stressed MOS devices and methods for their fabrication are provided. The stressed MOS device comprises a T-shaped gate electrode formed of a material having a first Young's modulus. The T-shaped gate electrode includes a first vertical portion and a second horizontal portion. The vertical portion overlies a channel region in an underlying substrate and has a first width; the horizontal portion has a second greater width. A tensile stressed film is formed overlying the second horizontal portion, and a material having a second Young's modulus less than the first Young's modulus fills the space below the second horizontal portion. The tensile stressed film imparts a stress on the horizontal portion of the gate electrode and this stress is transmitted through the vertical portion to the channel of the device. The stress imparted to the channel is amplified by the ratio of the second width to the first width.
  • Methods For Fabricating A Stressed Mos Device

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  • US Patent:
    7462524, Dec 9, 2008
  • Filed:
    Aug 16, 2005
  • Appl. No.:
    11/205797
  • Inventors:
    Igor Peidous - Fishkill NY, US
    Martin Gerhardt - Dresden, DE
    David E. Brown - Pleasant Valley NY, US
  • Assignee:
    Advanced Micro Devices, Inc. - Austin TX
  • International Classification:
    H01L 21/336
  • US Classification:
    438197, 438300, 438592
  • Abstract:
    Methods are provided for fabricating a stressed MOS device. One method comprises the steps of providing a substrate of a monocrystalline semiconductor material having a first lattice constant, and forming a conductive gate electrode overlying the substrate, the gate electrode having opposing sides and having a thickness. Sidewall spacers are formed on the opposing sides of the gate electrode and trenches are etched in the semiconductor substrate in alignment with the sidewall spacers. A portion of the thickness of the conductive gate electrode is also etched to leave a remaining portion of the conductive gate electrode. A stress inducing layer of material is grown on the remaining portion of the conductive gate electrode and filling the trenches, the stress inducing layer of material having a second lattice constant different than the first lattice constant.
  • Semiconductor Structures Including Multiple Crystallographic Orientations And Methods For Fabrication Thereof

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  • US Patent:
    7494918, Feb 24, 2009
  • Filed:
    Oct 5, 2006
  • Appl. No.:
    11/538963
  • Inventors:
    Byeong Y. Kim - LaGrangeville NY, US
    Xiaomeng Chen - Poughkeepsie NY, US
    Judson R. Holt - Wappingers Falls NY, US
    Christopher D. Sheraw - Poughkeepsie NY, US
    Linda Black - Wappingers Falls NY, US
    Igor Peidous - Fishkill NY, US
  • Assignee:
    International Business Machines Corporation - Armonk NY
    Advanced Micro Devices, Inc. (AMD) - Sunnyvale CA
  • International Classification:
    H01L 21/4763
    H01L 29/04
  • US Classification:
    438628, 257627, 257628, 438150, 438738, 438739
  • Abstract:
    Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.
  • Stress Enhanced Mos Transistor And Methods For Its Fabrication

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  • US Patent:
    7534689, May 19, 2009
  • Filed:
    Nov 21, 2006
  • Appl. No.:
    11/562209
  • Inventors:
    Rohit Pal - Fishkill NY, US
    Igor Peidous - Fishkill NY, US
    David Brown - Pleasant Valley NY, US
  • Assignee:
    Advanced Micro Devices, Inc. - Austin TX
  • International Classification:
    H01L 21/20
  • US Classification:
    438300, 438301, 438303, 438442, 438482, 257E21202, 257E21403, 257E21431, 257E21437, 257E21438, 257E29056, 257E29063, 257E29315
  • Abstract:
    A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

Resumes

Igor Peidous Photo 1

Materials Engineering

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Location:
1732 Washington Landing Dr, Eaton, OH 45320
Industry:
Semiconductors
Work:
Silfex, Inc. - A Division of Lam Research Corporation
Materials Engineering

Applied Materials Jan 2007 - Oct 2012
Director, Strategic Programs

Memc Electronic Materials Jan 2007 - Oct 2012
Director, Silicon-On-Insulator R and D

Amd Oct 2004 - Jan 2007
Member of Technical Staff

Dallas Semiconductor Mar 2001 - Oct 2004
Member of Technical Staff
Education:
National Research University of Electronic Technology (Miet) 1983 - 1986
Master of Science, Doctorates, Masters, Doctor of Philosophy, Electrical Engineering, Materials Science
Skills:
Semiconductors
Characterization
Failure Analysis
Thin Films
R&D
Metrology
Materials Science
Semiconductor Industry
Silicon
Electrical Engineering
Cmos
Design of Experiments
Vlsi
Mixed Signal
Physics
Program Management
Integrated Circuits
Ic
Manufacturing
Research and Development
Very Large Scale Integration
Yield
Igor Peidous Photo 2

Igor Peidous

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