Ian M Steiner

US Patent:

7991963, Aug 2, 2011

Filed:

Dec 31, 2007

Appl. No.:

12/006326

Inventors:

Ian M. Steiner - Hillsboro OR, US
Saurabh Tiwari - Bangalore, IN
Kai Cheng - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711133, 711118, 711141, 711159

Abstract:

In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing coherency information associated with the demanded cache line from a memory unit by bringing in from a memory page in which the demanded cache line is stored, the memory page also including a directory line having coherency information corresponding to the demanded cache line; reading data associated with the demanded cache line in accordance with the coherency information; and returning the data to the processor.

US Patent:

8429367, Apr 23, 2013

Filed:

Dec 28, 2007

Appl. No.:

11/965953

Inventors:

James W. Alexander - Hillsboro OR, US
Son H. Lam - Puyallup WA, US
Devadatta V. Bodas - Federal Way WA, US
Krishna Kant - Portland OR, US
Kai Cheng - Portland OR, US
Ian M. Steiner - Hillsboro OR, US
Gopikrishna Jandhyala - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/04

US Classification:

711169, 711 5, 711167, 713500, 713600, 3652331

Abstract:

Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.

US Patent:

20090171875, Jul 2, 2009

Filed:

Dec 28, 2007

Appl. No.:

11/965955

Inventors:

James W. Alexander - Hillsboro OR, US
Son H. Lam - Puyallup WA, US
Devadatta V. Bodas - Federal Way WA, US
Krishna Kant - Portland OR, US
Kai Cheng - Portland OR, US
Ian M. Steiner - Hillsboro OR, US

International Classification:

G06N 5/02

US Classification:

706 46

Abstract:

Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed.

US Patent:

20120144217, Jun 7, 2012

Filed:

Dec 15, 2011

Appl. No.:

13/326605

Inventors:

Krishnakanth V. Sistla - Beaverton OR, US
Mark Rowland - Beaverton OR, US
Ankush Varma - Hillsboro OR, US
Ian M. Steiner - Hillsboro OR, US
Matthew Bace - North Andover MA, US
Daniel Borkowski - Lunenburg MA, US
Vivek Garg - Folsom CA, US
Cagdas Akturan - Hillsboro OR, US
Avinash N. Ananthakrishnan - Hillsboro OR, US

International Classification:

G06F 1/32
G06F 1/00

US Classification:

713320, 713300

Abstract:

In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

US Patent:

20120204042, Aug 9, 2012

Filed:

Dec 15, 2011

Appl. No.:

13/326586

Inventors:

Krishnakanth V. Sistla - Beaverton OR, US
Jeremy Shrall - Portland OR, US
Stephen H. Gunther - Beaverton OR, US
Efraim Rotem - Haifa, IL
Alon Naveh - Ramat Hasharon, IL
Eliezer Weissmann - Haifa, IL
Anil Aggarwal - Portland OR, US
Martin T. Rowland - Beaverton OR, US
Ankush Varma - Hillsboro OR, US
Ian M. Steiner - Hillsboro OR, US
Matthew Bace - North Andover MA, US
Avinash N. Ananthakrishnan - Hillsboro OR, US
Jason Brandt - Austin TX, US

International Classification:

G06F 1/32
G06F 1/26

US Classification:

713310, 713320

Abstract:

In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

US Patent:

20130179706, Jul 11, 2013

Filed:

Mar 1, 2013

Appl. No.:

13/782473

Inventors:

Krishnakanth V. Sistla - Beaverton OR, US
Jeremy Shrall - Portland OR, US
Stephen H. Gunther - Beaverton OR, US
Efraim Rotem - Haifa, IL
Alon Naveh - Ramat Hasharon, IL
Eliezer Weissmann - Haifa, IL
Anil Aggarwal - Portland OR, US
Martin T. Rowland - Beaverton OR, US
Ankush Varma - Hillsboro OR, US
Ian M. Steiner - Hillsboro OR, US
Matthew Bace - North Andover MA, US
Avinash N. Ananthakrishnan - Hillsboro OR, US
Jason Brandt - Austin TX, US

International Classification:

G06F 1/26

US Classification:

713310

Abstract:

In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

US Patent:

20220413720, Dec 29, 2022

Filed:

Jun 25, 2021

Appl. No.:

17/359334

Inventors:

- Santa Clara CA, US
Ian Steiner - Portland OR, US
Vasudevan Srinivasan - Portland OR, US
Ankush Varma - Portland OR, US
Nikhil Gupta - Portland OR, US
Stanley Chen - Portland OR, US

International Classification:

G06F 3/06

Abstract:

In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.

US Patent:

20210294400, Sep 23, 2021

Filed:

Jun 3, 2021

Appl. No.:

17/338547

Inventors:

- Santa Clara CA, US
Lokesh Sharma - Bangalore, IN
Buck Gremel - Olympia WA, US
Ian Steiner - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/20
G06F 1/3234

Abstract:

In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.