Hung Lieu Lin

US Patent:

8212706, Jul 3, 2012

Filed:

Jun 24, 2010

Appl. No.:

12/822443

Inventors:

Hung Sheng Lin - San Jose CA, US
Shafiq Jamal - Gilroy CA, US
Shingo Hatanaka - San Jose CA, US
Xiaoyue Wang - Santa Clara CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03M 1/34

US Classification:

341164, 341118, 341120, 341155, 341165

Abstract:

In one embodiment, a method receives an analog input voltage. The method also receives a threshold from a plurality of thresholds. A comparator performs a comparison of the input voltage with the received threshold and outputs an output value based on the comparison of the analog input voltage with the received threshold. The output value is for converting the analog input voltage to a digital value. The method determines if the threshold should be adjusted based on the comparison and adjusts the threshold when it is determined the threshold should be adjusted.

US Patent:

8436760, May 7, 2013

Filed:

Sep 15, 2010

Appl. No.:

12/882496

Inventors:

Shingo Hatanaka - San Jose CA, US
Shafiq M. Jamal - Gilroy CA, US
Hung Sheng Lin - San Jose CA, US
Ovidiu Carnu - San Francisco CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03M 1/38

US Classification:

341161, 341118, 341122, 341155, 341156

Abstract:

The present disclosure includes systems and techniques relating to low power current-voltage mixed ADC architecture. In some implementations, an apparatus includes sample and hold circuitry, at least one ADC module configured to generate a first digital output based on a first analog input provided to the sample and hold circuitry, and current generation circuitry configured to modulate an analog output of the sample and hold circuitry to generate a residue output corresponding to the first analog input absent at least a portion corresponding to the first digital output, and to provide the residue output as a second analog input to further circuitry to generate a second digital output.

US Patent:

7994961, Aug 9, 2011

Filed:

Jun 9, 2009

Appl. No.:

12/480977

Inventors:

Hung Sheng Lin - San Jose CA, US
Ovidiu Carnu - San Francisco CA, US
Shingo Hatanaka - San Jose CA, US

Assignee:

Marvell International Ltd

International Classification:

H03M 1/12

US Classification:

341172, 341161

Abstract:

Methods and systems are described for providing an analog-to-digital converter that uses reduced power and supply voltage. The analog-to-digital converter includes a sample phase configured to sample an incoming analog signal having an input signal range and compare the incoming analog signal to a reference voltage. The analog-to-digital converter also includes a feedback phase wherein the feedback phase receives sampled signal data corresponding to the incoming analog signal from the sample phase and is configured to produce an output signal comprising an output signal range, wherein the output signal range is equal to one half of the input signal range, and wherein the analog-to-digital converter has a feedback factor that is substantially greater than ⅓.

US Patent:

20120286393, Nov 15, 2012

Filed:

May 7, 2012

Appl. No.:

13/465605

Inventors:

Hung Sheng Lin - San Jose CA, US
Shingo Hatanaka - San Jose CA, US
Shafiq M. Jamal - Pleasanton CA, US

International Classification:

H01L 29/92

US Classification:

257532, 257E29343

Abstract:

A finger metal oxide metal (MOM) capacitor includes an outer conducting structure defined in a plurality of metal layers and a plurality of via layers of an integrated circuit. First and second side portions include a plurality of first and second finger sections extending in the plurality of metal layers and first and second hole vias connecting the first and second finger sections, respectively. A middle portion connects the first and second side portions. An inner conducting structure is defined in the plurality of metal layers and the plurality of via layers of the integrated circuit. A plurality of “T”-shaped sections are defined in the plurality of metal layers and third hole vias connecting the plurality of “T”-shaped sections. Middle portions of the plurality of “T”-shaped sections extend towards the middle portion and between the first side portion and the second side portion of the outer conducting structure.

US Patent:

20220383817, Dec 1, 2022

Filed:

Aug 9, 2022

Appl. No.:

17/884297

Inventors:

- Cupertino CA, US
Hung Sheng Lin - San Jose CA, US
Shih Chang Chang - Cupertino CA, US
Shinya Ono - Santa Clara CA, US

International Classification:

G09G 3/3233
H01L 29/786
G09G 3/3266
G09G 3/3275
H01L 27/12

Abstract:

A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.

US Patent:

20210304673, Sep 30, 2021

Filed:

Mar 3, 2021

Appl. No.:

17/191009

Inventors:

- Cupertino CA, US
Haifeng Li - Campbell CA, US
Sinan Alousi - Campbell CA, US
Marc Joseph DeVincentis - Palo Alto CA, US
Yafei Bi - Los Altos Hills CA, US
Hung Sheng Lin - San Jose CA, US
Yi Qiao - San Jose CA, US
Paolo Sacchetto - Cupertino CA, US
Weijun Yao - Saratoga CA, US
Pierre-Yves Emelie - Mountain View CA, US
Maofeng Yang - Santa Clara CA, US
Yue Jack Chu - Cupertino CA, US

International Classification:

G09G 3/3233

Abstract:

A system may include an electronic display panel having pixels, where each pixel may emit light based on a respective programming signal. The system may include a memory storing a map. The processing circuitry may determine a function for each pixel from the map. The processing circuitry may determine a respective control signal based on the function and a target brightness level for each pixel to generate multiple control signals, where the respective control signal is used to generate the respective programing signal for each pixel. The processing circuitry may determine a scaling factor based at least in part on the first map and may scale at least a subset of the multiple control signals based at least in part on the scaling factor.

US Patent:

20210225283, Jul 22, 2021

Filed:

Apr 5, 2021

Appl. No.:

17/222844

Inventors:

- Cupertino CA, US
Hung Sheng Lin - San Jose CA, US
Shih Chang Chang - Cupertino CA, US
Shinya Ono - Santa Clara CA, US

International Classification:

G09G 3/3233
H01L 29/786
G09G 3/3266
G09G 3/3275
H01L 27/12

Abstract:

A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.

US Patent:

20210150950, May 20, 2021

Filed:

Aug 31, 2018

Appl. No.:

16/644932

Inventors:

Junhua TAN - Cupertino CA, US
Chin-Wei LIN - Cupertino CA, US
Hung Sheng LIN - Cupertino CA, US
Hyunsoo KIM - Cupertino CA, US
Hyunwoo NHO - Cupertino CA, US
Injae HWANG - Cupertino CA, US
Jesse A. RICHMOND - Cupertino CA, US
Jie Won RYU - Cupertino CA, US
Kingsuk BRAHMA - Cupertino CA, US
Shengkui GAO - Cupertino CA, US
Shiping SHEN - Cupertino CA, US
Sun-Il CHANG - Cupertino CA, US
Yafei BI - Cupertino CA, US
Myungjoon CHOI - Cupertino CA, US
Chaohao WANG - Cupertino CA, US
Weichuan YAO - Cupertinp CA, US
- Cupertino CA, US

International Classification:

G09G 3/00

Abstract:

Electronic devices and methods for compensating for aging or other effects in a display during a non-transmitting state (off state) of the display. Sensing may include emissive element sensing of the display and/or thin film transistor sensing of the display. Compensating for the effects may preserve or increase a uniformity of transmission of the display.