Hideki Ido

US Patent:

20110153983, Jun 23, 2011

Filed:

Dec 22, 2009

Appl. No.:

12/644440

Inventors:

Christopher J. Hughes - Cupertino CA, US
Yen-Kuang (Y.K.) Chen - Cupertino CA, US
Mayank Bomb - Hillsboro OR, US
Jason W. Brandt - Austin TX, US
Mark J. Buxton - Chandler AZ, US
Mark J. Charney - Lexington MA, US
Srinivas Chennupaty - Portland OR, US
Jesus Corbal - Barcelona, ES
Martin G. Dixon - Portland OR, US
Milind B. Girkar - Sunnyvale CA, US
Jonathan C. Hall - Hillsboro OR, US
Hideki (Saito) Ido - Sunnyvale CA, US
Peter Lachner - Heroldstatt, DE
Gilbert Neiger - Portland OR, US
Chris J. Newburn - South Beloit IL, US
Rajesh S. Parthasarathy - Hillsboro OR, US
Bret L. Toll - Hillsboro OR, US
Robert Valentine - Kiryat Trvon, IL
Jeffrey G. Wiedemeier - Austin TX, US

International Classification:

G06F 9/38
G06F 15/76
G06F 9/06
G06F 12/08

US Classification:

712 22, 712244, 711125, 712E09049, 712E09003, 711E12017

Abstract:

According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

US Patent:

20120117552, May 10, 2012

Filed:

Nov 9, 2010

Appl. No.:

12/942543

Inventors:

Rakesh Krishnaiyer - Milpitas CA, US
Hideki Saito Ido - Sunnyvale CA, US
Ernesto Su - Campbell CA, US
John L. Ng - San Jose CA, US
Jin Lin - San Jose CA, US
Xinmin Tian - Union City CA, US
Robert Y. Geva - Cupertino CA, US

International Classification:

G06F 9/45

US Classification:

717160, 717159

Abstract:

Methods to improve optimization of compilation are presented. In one embodiment, a method includes identifying one or more optimization speculations with respect to a code region and speculatively performing transformation on an intermediate representation of the code region in accordance with an optimization speculation. The method includes generating an advice message corresponding to the optimization speculation and displaying the advice message if the optimization speculation results in an improved compilation result.

US Patent:

20120166761, Jun 28, 2012

Filed:

Dec 22, 2010

Appl. No.:

12/976616

Inventors:

Christopher J. Hughes - Santa Clara CA, US
Mark J. Charney - Lexington MA, US
Yen-Kuang Chen - Cupertino CA, US
Jesus Corbal - Barcelona, ES
Andrew T. Forsyth - Kirkland WA, US
Milind B. Girkar - Sunnyvale CA, US
Jonathan C. Hall - Hillsboro OR, US
Hideki Ido - Sunnyvale CA, US
Robert Valentine - Kiryat Tivon, IL
Jeffrey Wiedemeier - Austin TX, US

International Classification:

G06F 9/30

US Classification:

712 7, 712E09016

Abstract:

A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.

US Patent:

20210397454, Dec 23, 2021

Filed:

Jun 18, 2020

Appl. No.:

16/905914

Inventors:

- Santa Clara CA, US
Hideki Ido - Sunnyvale CA, US
Ilya Burylov - Nizhny Novogorod NGR, RU
Ruslan Arutyunyan - Nizhny Novogorod, RU

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/38
G06F 9/22
G06F 9/30

Abstract:

Methods and apparatus relating to techniques for vectorizing loops with backward cross-iteration dependencies are described. In an embodiment, execution of one or more instructions resolves a cross-iteration dependency of one or more operations of a loop. The execution of the one or more instructions resolves the cross-iteration dependency of the one or more operations based at least in part on one or more distance count computations to a preceding iteration of the loop. Other embodiments are also disclosed and claimed.

US Patent:

20210034344, Feb 4, 2021

Filed:

Oct 19, 2020

Appl. No.:

17/074336

Inventors:

- Santa Clara CA, US
Hideki Ido - Sunnyvale CA, US
Eric N. Garcia - Redwood City CA, US

International Classification:

G06F 8/41

Abstract:

Methods, apparatus, systems, and articles of manufacture are disclosed to improve loop optimization with predictable recurring memory reads (PRMRs). An example apparatus includes memory, and first processor circuitry to execute first instructions to at least identify one or more optimizations to convert a first loop into a second loop based on converting PRMRs of the first loop into loop-invariant PRMRs, the converting of the PRMRs in response to a quantity of the PRMRs satisfying a threshold, the second loop to execute in a single iteration corresponding to a quantity of iterations of the first loop, determine one or more optimization parameters based on the one or more optimizations, and compile second instructions based on the first processor circuitry processing the first loop based on the one or more optimization parameters associated with the one or more optimizations, the second instructions to be executed by the first or second processor circuitry.

US Patent:

20200210183, Jul 2, 2020

Filed:

Mar 6, 2020

Appl. No.:

16/811011

Inventors:

- Santa Clara CA, US
Mikhail Plotnikov - Nizhny Novgorod, RU
Hideki Ido - Sunnyvale CA, US
Ruslan Arutyunyan - Nizhny Novgorod, RU

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/30
G06F 9/32

Abstract:

Systems, apparatuses and methods may provide for technology that identifies that an iterative loop includes a first code portion that executes in response to a condition being satisfied, generates a first vector mask that is to represent one or more instances of the condition being satisfied for one or more values of a first vector of values, and one or more instances of the condition being unsatisfied for the first vector of values, where the first vector of values is to correspond to one or more first iterations of the iterative loop, and conducts a vectorization process of the iterative loop based on the first vector mask.

US Patent:

20190278577, Sep 12, 2019

Filed:

Jul 1, 2016

Appl. No.:

16/304644

Inventors:

- Santa Clara CA, US
Hideki IDO - Sunnyvale CA, US
Xinmin TIAN - Fremont CA, US
Sergey PREIS - Novosibirsk, RU
Milind B. GIRKAR - Sunnyvale CA, US
Maxim SHUTOV - Nizhny Novgorod, RU

International Classification:

G06F 8/41

Abstract:

Methods, apparatus, and system to optimize compilation of source code into vectorized compiled code, notwithstanding the presence of output dependencies which might otherwise preclude vectorization.

US Patent:

20190042224, Feb 7, 2019

Filed:

Sep 11, 2018

Appl. No.:

16/128275

Inventors:

- Santa Clara CA, US
Hideki Ido - Sunnyvale CA, US
Eric N. Garcia - Redwood City CA, US

International Classification:

G06F 8/41

Abstract:

Methods, apparatus, systems, and articles of manufacture are disclosed to improve loop optimization with predictable recurring memory reads (PRMRs). An example apparatus includes an optimizer including an optimization scenario manager to generate an optimization plan associated with a loop and corresponding optimization parameters, the optimization plan including a set of one or more optimizations, an optimization scenario analyzer to identify the optimization plan as a candidate optimization plan when a quantity of PRMRs included in the loop is greater than a threshold, and a parameter calculator to determine the optimization parameters based on the candidate optimization plan, and a code generator to generate instructions to be executed by a processor, the instructions based on processing the loop with the one or more optimizations included in the candidate optimization plan.