Guy R Dupenloup

US Patent:

7178117, Feb 13, 2007

Filed:

Apr 8, 2004

Appl. No.:

10/821466

Inventors:

Ninh Ngo - San Jose CA, US
Guy Dupenloup - Redwood City CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50
G06F 9/45
H03K 17/693

US Classification:

716 5, 716 1, 716 4, 716 16

Abstract:

An RTL representation for a LAB is generated. A full chip RTL model is then generated using a plurality of the LAB RTLs. Using the full chip RTL model, a full chip simulation of the PLD chip is performed to verify and debug the electronic design.

US Patent:

7308659, Dec 11, 2007

Filed:

Aug 14, 2003

Appl. No.:

10/642084

Inventors:

Gopinath Rangan - Milpitas CA, US
Guy Dupenloup - Redwood City CA, US
Wira Gunawan - Santa Clara CA, US
Khai Nguyen - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 5, 716 4, 716 6, 703 16

Abstract:

The present invention is directed to reducing errors due to floating values introduced during tristate and contention when modeling a register in RTL. In one embodiment, the floating values are replaced by predetermined desired values corresponding to the floating values which are both stored in a lookup table. In another embodiment, when a floating value is detected, that value is ignored and the previous clock value is retained.

US Patent:

7506017, Mar 17, 2009

Filed:

May 25, 2004

Appl. No.:

10/853427

Inventors:

Guy Dupenloup - Redwood City CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 7/52

US Classification:

708620, 708625

Abstract:

A verifiable duplex multiplier circuit is provided. In one mode, the circuitry of the duplex multiplier functions as an N-bit×N-bit multiplier. In another mode, the circuitry of the duplex multiplier operates as dual N/2-bit×N/2-bit multipliers. Because the same circuitry can be used to serve as both an N×N multiplier and as dual N/2×N/2 multipliers, integrated circuit resources are conserved. The duplex multiplier circuitry uses an architecture that can be automatically synthesized using a logic synthesis tool. Verification operations can be performed using logic-equivalency error checking tools. Exhaustive verification is possible using this approach, even when relatively large duplex multipliers (e. g. , duplex multipliers with N values of 16 or more) are used.

US Patent:

8095899, Jan 10, 2012

Filed:

Feb 25, 2009

Appl. No.:

12/393019

Inventors:

Guy Dupenloup - Redwood City CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50

US Classification:

716103, 716100, 716101, 716104

Abstract:

A verifiable duplex multiplier circuit is provided. In one mode, the circuitry of the duplex multiplier functions as an N-bit×N-bit multiplier. In another mode, the circuitry of the duplex multiplier operates as dual N/2-bit×N/2-bit multipliers. Because the same circuitry can be used to serve as both an N×N multiplier and as dual N/2×N/2 multipliers, integrated circuit resources are conserved. The duplex multiplier circuitry uses an architecture that can be automatically synthesized using a logic synthesis tool. Verification operations can be performed using logic-equivalency error checking tools. Exhaustive verification is possible using this approach, even when relatively large duplex multipliers (e. g. , duplex multipliers with N values of 16 or more) are used.

US Patent:

8336007, Dec 18, 2012

Filed:

Jan 5, 2012

Appl. No.:

13/343898

Inventors:

Guy Dupenloup - Redwood City CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50

US Classification:

716103, 716100, 716101, 716104

Abstract:

A verifiable duplex multiplier circuit is provided. In one mode, the circuitry of the duplex multiplier functions as an N-bit×N-bit multiplier. In another mode, the circuitry of the duplex multiplier operates as dual N/2-bit×N/2-bit multipliers. Because the same circuitry can be used to serve as both an N×N multiplier and as dual N/2×N/2 multipliers, integrated circuit resources are conserved. The duplex multiplier circuitry uses an architecture that can be automatically synthesized using a logic synthesis tool. Verification operations can be performed using logic-equivalency error checking tools. Exhaustive verification is possible using this approach, even when relatively large duplex multipliers (e. g. , duplex multipliers with N values of 16 or more) are used.