George Pete Imthurn

US Patent:

6372592, Apr 16, 2002

Filed:

Dec 18, 1996

Appl. No.:

08/768694

Inventors:

Stephen D. Russell - San Diego CA
Douglas A. Sexton - San Diego CA
Bruce W. Offord - San Diego CA
George P. Imthurn - San Diego CA

Assignee:

United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01L 21336

US Classification:

438308, 438149, 438166, 438795, 257 57, 257 66, 257347, 257352, 257410, 257411, 257412

Abstract:

A method for making a self-aligned FET with an electrically active mask comprises the steps of forming a semiconductor layer on an insulating substrate, forming an electrically nonconductive oxide layer on the semiconductor layer, forming an electrically conductive metal layer on the oxide layer, patterning the metal layer and the oxide layer to form an electrically active gate on semiconductor layer, introducing dopants into the semiconductor layer to form a source region and a drain region masked by the metal gate, and illuminating the source and the drain regions with a pulsed excimer laser having a wavelength from about 150 nm to 350 nm to anneal the source region and the drain region.

US Patent:

6703647, Mar 9, 2004

Filed:

Apr 22, 2002

Appl. No.:

10/131442

Inventors:

Graham A. Garcia - San Diego CA
George P. Imthurn - San Diego CA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01L 310328

US Classification:

257184, 257108, 257109, 257164, 257197, 257461, 257560, 257563

Abstract:

A high gain phototransistor uses lateral and vertical transistor structures and a triple base. The base regions of two vertical structures are in the bulk of a semiconductor substrate while the base of a single lateral structure is adjacent a light receiving phototransistor surface. Minority carrier generation extends from the base region of the lateral transistor to the base regions of the vertical transistors and is present in the vertical regions within a diffusion length of the optically generated carriers of the lateral base. The bases of all three transistor structures are electrically connected. The collector electrodes of one of the vertical structures and the lateral structure are electrically connected, while the emitter electrodes of the other of the vertical structures and the lateral structures are electrically connected. Finally, the remaining vertical collector and emitter electrodes are electrically connected via a buried layer adjacent the phototransistor wafer substrate.

US Patent:

7411250, Aug 12, 2008

Filed:

May 13, 2004

Appl. No.:

10/846864

Inventors:

Anthony M. Miscione - Ramona CA, US
George Imthurn - San Diego CA, US
Eugene F. Lyons - Santee CA, US
Michael A. Stuber - Carlsbad CA, US

Assignee:

Peregrine Semiconductor Corporation - San Diego CA

International Classification:

H01L 27/01

US Classification:

257352, 257E21704, 257E27111

Abstract:

A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer.

US Patent:

7524710, Apr 28, 2009

Filed:

Jun 6, 2008

Appl. No.:

12/134681

Inventors:

Anthony M. Miscione - Ramona CA, US
George Imthurn - San Diego CA, US
Eugene F. Lyons - Santee CA, US
Michael A. Stuber - Carlsbad CA, US

Assignee:

Peregrine Semiconductor Corporation - San Diego CA

International Classification:

H01L 27/01

US Classification:

438154, 438149, 438151, 438164, 438166, 257347, 257352, 257E2141, 257E2161, 257E21704

Abstract:

A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer.

US Patent:

7890891, Feb 15, 2011

Filed:

Sep 14, 2006

Appl. No.:

11/520912

Inventors:

Michael A. Stuber - Carlsbad CA, US
Christopher N. Brindle - Poway CA, US
Dylan J. Kelly - San Diego CA, US
Clint L. Kemerling - Escondido CA, US
George P. Imthurn - San Diego CA, US
Robert B. Welstand - San Diego CA, US
Mark L. Burgener - San Diego CA, US
Alexander Dribinsky - Naperville IL, US
Tae Youn Kim - San Diego CA, US

Assignee:

Peregrine Semiconductor Corporation - San Diego CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 2

Abstract:

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET.

US Patent:

7910993, Mar 22, 2011

Filed:

Jul 10, 2006

Appl. No.:

11/484370

Inventors:

Christopher N. Brindle - Poway CA, US
Michael A. Stuber - Carlsbad CA, US
Dylan J. Kelly - San Diego CA, US
Clint L. Kemerling - Escondido CA, US
George P. Imthurn - San Diego CA, US
Robert B. Welstand - San Diego CA, US
Mark L. Burgener - San Diego CA, US

Assignee:

Peregrine Semiconductor Corporation - San Diego CA

International Classification:

H01L 27/12

US Classification:

257347

Abstract:

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

US Patent:

8129787, Mar 6, 2012

Filed:

Mar 22, 2011

Appl. No.:

13/053211

Inventors:

Christopher N. Brindle - Poway CA, US
Michael A. Stuber - Carlsbad CA, US
Dylan J. Kelly - San Diego CA, US
Clint L. Kemerling - Escondido CA, US
George P. Imthurn - San Diego CA, US
Robert B. Welstand - San Diego CA, US
Mark L. Burgener - San Diego CA, US

Assignee:

Peregrine Semiconductor Corporation - San Diego CA

International Classification:

H01L 27/12

US Classification:

257347

Abstract:

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

US Patent:

8405147, Mar 26, 2013

Filed:

Mar 5, 2012

Appl. No.:

13/412529

Inventors:

Christopher N. Brindle - Poway CA, US
Michael A. Stuber - Carlsbad CA, US
Dylan J. Kelly - San Diego CA, US
Clint L. Kemerling - Escondido CA, US
George P. Imthurn - San Diego CA, US
Robert B. Welstand - San Diego CA, US
Mark L. Burgener - San Diego CA, US

Assignee:

Peregrine Semiconductor Corporation - San Diego CA

International Classification:

H04B 1/28
H01L 29/76
H01L 7/20
H04M 1/00

US Classification:

257341

Abstract:

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOT MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.