Geoffrey Carlos Stutzin

US Patent:

6479394, Nov 12, 2002

Filed:

May 3, 2000

Appl. No.:

09/564327

Inventors:

Dmitri A. Choutov - San Jose CA
Alexander Kalnitsky - Portland OR
Geoffrey C. Stutzin - San Carlos CA

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H01L 21302

US Classification:

438714, 438697, 438700, 438719, 438720, 438724

Abstract:

A method of etching dissimilar materials having interfaces at non-perpendicular angles to the direction of the etch propagation that results in a low selectivity etch in order to achieve an improved planarized etched surface. The method includes the step of subjecting the dissimilar materials to a process gas mixture that includes a first gas that dominates the etching of a first material and a second gas that dominates the etching of a second material. The flow rates for the first and second materials are selected, along with other parameters of the plasma etch apparatus, to substantially equalize the etching rates for the two materials. This method is particularly useful to achieve a low-selective etching of materials having interfaces that are at a non-perpendicular angle with respect to the etch propagation.

US Patent:

6593200, Jul 15, 2003

Filed:

Nov 20, 2001

Appl. No.:

09/989649

Inventors:

Alexander Kalnitsky - Portland OR
Dmitri A. Choutov - San Jose CA
Geoffrey C. Stutzin - San Carlos CA
Robert F. Scheer - Portland OR

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H01L 21331

US Classification:

438363, 438360

Abstract:

A method of forming a semiconductor device with an inductor and/or high speed interconnect. The method comprises forming an epitaxial layer over the substrate, forming an opening through the epitaxial layer to expose an underlying region of the substrate, forming a first dielectric material within the opening of the epitaxial layer, planarizing the first dielectric layer, forming a second dielectric material layer over the first dielectric material layer, and then forming a metallized inductor over the second dielectric material layer above the opening of the epitaxial layer. In this case, since the inductor and the high speed interconnect do not overlie the conductive epitaxial layer, the degradation in the Q-factor of the inductor, loss characteristics of the high speed interconnect, and âcross-talkâ between conductors are substantially reduced. The resulting semiconductor device is also disclosed.

US Patent:

63034131, Oct 16, 2001

Filed:

May 3, 2000

Appl. No.:

9/564178

Inventors:

Alexander Kalnitsky - Portland OR
Dmitri A. Choutov - San Jose CA
Robert F. Scheer - Portland OR
Fanling H. Yang - Beaverton OR
Thomas W. Dobson - Portland OR
Tadanori Yamaguchi - Portland OR
Geoffrey C. Stutzin - San Carlos CA
Ken Liao - Beaverton OR

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H01L 2100

US Classification:

438151

Abstract:

A method of forming a shallow-deep trench isolation (SDTI) is provided that includes the steps of forming a pair of deep trenches through a silicon on insulator (SOI) layer without substantially disturbing an underlying buried oxide (BOX) layer. Once the deep trenches are formed, the trenches are filed with suitable electrical isolating materials, such as undoped poly-silicon or dielectric material, and etched back to obtain a substantially planarized top surface. Subsequently, an active nitride layer is deposited on the planarized top surface, and then a pair of shallow trenches are formed. The shallow trenches are formed using a low selectivity etch to uniformly etch a deep trench liner oxide, the SOI layer and the electrical isolating material which have interfaces at non-perpendicular angles with respect to the direction of the etching. Once the shallow and deep trenches are formed, subsequent processing including filling the shallow trench, annealing and chemical-mechanical polishing can be performed.