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Gennady S Feygin

age ~61

from San Diego, CA

Also known as:
  • Gennady M Feygin
  • Gennady Seygin
  • Gennady Feygan
  • Gennady Feyfin
  • Feygin Gennady
  • Y D
Phone and address:
3420 Lady Hill Rd, San Diego, CA 92130

Gennady Feygin Phones & Addresses

  • 3420 Lady Hill Rd, San Diego, CA 92130
  • 4533 Meadow Ridge Dr, Plano, TX 75093
  • 10 Falcon Rd, Livingston, NJ 07039
  • 6919 Flintcove Dr, Dallas, TX 75248 • 972-960-8732
  • Edison, NJ
  • Scotch Plains, NJ
  • Colton, TX
  • 10 Falcon Rd, Livingston, NJ 07039 • 973-204-7762

Work

  • Position:
    Machine Operators, Assemblers, and Inspectors Occupations

Education

  • Degree:
    Associate degree or higher

Us Patents

  • On-Line Offset Cancellation In Flash A/D With Interpolating Comparator Array

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  • US Patent:
    6420983, Jul 16, 2002
  • Filed:
    May 25, 2000
  • Appl. No.:
    09/578283
  • Inventors:
    Gennady Feygin - Livingston NJ
    David A. Martin - Atlantic Highlands NJ
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H03M 106
  • US Classification:
    341118, 341120
  • Abstract:
    A method for performing an auto-zero function in a flash analog to digital converter (âADCâ), the ADC including a reference voltage circuit, providing a plurality of evenly spaced analog reference voltages, and a plurality of system voltage comparators for comparing an input voltage against the reference voltages and providing an indication of which reference voltage corresponds to the input voltage. In the method the following steps are performed. A plurality of redundant voltage comparators are provided. A subset of the plurality of system voltage comparators are selected. Auto-zero is performed on the selected comparators, and the redundant comparators are used in the place of the selected comparators. The outputs of the main comparator array and the extra comparators are combined to produce a final digital output.
  • Active Removal Of Aliasing Frequencies In A Decimating Structure By Changing A Decimation Ratio In Time And Space

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  • US Patent:
    6856925, Feb 15, 2005
  • Filed:
    Oct 11, 2002
  • Appl. No.:
    10/269349
  • Inventors:
    Khurram Muhammad - Richardson TX, US
    Robert B. Staszewski - Garland TX, US
    Gennady Feygin - Dallas TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    G06F019/00
  • US Classification:
    702 75, 455296
  • Abstract:
    When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer with capacitor banks and that are controlled by a digital control unit with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
  • Active Removal Of Aliasing Frequencies In A Decimating Structure By Changing A Decimation Ratio In Time And Space

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  • US Patent:
    7103489, Sep 5, 2006
  • Filed:
    Aug 23, 2004
  • Appl. No.:
    10/924303
  • Inventors:
    Khurram Muhammad - Richardson TX, US
    Robert B. Staszewski - Garland TX, US
    Gennady Feygin - Dallas TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    G06F 19/00
  • US Classification:
    702 75, 324 7624
  • Abstract:
    When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer with capacitor banks and that are controlled by a digital control unit with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
  • Gain Calibration Of A Digital Controlled Oscillator

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  • US Patent:
    7183860, Feb 27, 2007
  • Filed:
    Jun 10, 2005
  • Appl. No.:
    11/149859
  • Inventors:
    Robert B. Staszewski - Garland TX, US
    Gennady Feygin - Plano TX, US
    Oren E. Eliezer - Plano TX, US
    Dirk Leipold - Plano TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H03C 3/06
    H03L 7/091
    H03L 7/099
  • US Classification:
    331 1A, 331 14, 331 17, 331 25, 327159, 332127, 375376
  • Abstract:
    A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.
  • Gain Calibration Of A Digital Controlled Oscillator

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  • US Patent:
    7466207, Dec 16, 2008
  • Filed:
    Jan 3, 2007
  • Appl. No.:
    11/619529
  • Inventors:
    Robert B. Staszewski - Garland TX, US
    Gennady Feygin - Plano TX, US
    Oren E. Eliezer - Plano TX, US
    Dirk Leipold - Plano TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H03C 3/06
    H03L 7/091
    H03L 7/099
  • US Classification:
    331 1A, 331 14, 331 17, 331 25, 327159, 332127, 375376
  • Abstract:
    A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.
  • Active Removal Of Aliasing Frequencies In A Decimating Structure By Changing A Decimation Ratio In Time And Space

    view source
  • US Patent:
    7466777, Dec 16, 2008
  • Filed:
    Aug 23, 2004
  • Appl. No.:
    10/924159
  • Inventors:
    Khurram Muhammad - Richardson TX, US
    Robert B. Staszewski - Garland TX, US
    Gennady Feygin - Dallas TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H03D 1/04
  • US Classification:
    375346, 375350
  • Abstract:
    When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer with capacitor banks and that are controlled by a digital control unit with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
  • Active Removal Of Aliasing Frequencies In A Decimating Structure By Changing A Decimation Ratio In Time And Space

    view source
  • US Patent:
    7647192, Jan 12, 2010
  • Filed:
    Aug 23, 2004
  • Appl. No.:
    10/924297
  • Inventors:
    Khurram Muhammad - Dallas TX, US
    Robert B. Staszewski - Delft, NL
    Gennady Feygin - Dallas TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    G06F 19/00
  • US Classification:
    702 75
  • Abstract:
    When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer with capacitor banks and that are controlled by a digital control unit with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
  • Method And Apparatus To Provide Digitally Controlled Crystal Oscillators

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  • US Patent:
    7808327, Oct 5, 2010
  • Filed:
    Aug 7, 2006
  • Appl. No.:
    11/500083
  • Inventors:
    Gennady Feygin - Plano TX, US
    Khurram Muhammad - Dallas TX, US
    Chih-Ming Hung - McKinney TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H03B 27/00
  • US Classification:
    331 46, 331 47, 331 48, 331 55, 331 57
  • Abstract:
    Methods and systems to provide digitally controlled crystal oscillators are disclosed. One example method includes determining a state of an oscillator system and selecting a first output of a digitally controlled crystal oscillator or a second output of a second oscillator based on the determination. In an example implementation, the second oscillator is a ring oscillator.

Resumes

Gennady Feygin Photo 1

Principal Design Engineer

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Location:
San Diego, CA
Industry:
Semiconductors
Work:
Samsung Electronics since Jan 2011
Principal Design Engineer

Dongbu Hitek USA 2009 - Feb 2011
Senior Design Engineer

Texas Instruments Feb 2001 - 2009
Senior Design Engineer

Texas Instruments Aug 1998 - Oct 2002
Design Engineer

Texas Instruments Oct 1995 - Aug 1998
Design Engineer
Education:
University of Toronto 1988 - 1995
PhD and MASc, Electrical and Computer Engineering
University of Alberta 1981 - 1986
BScEE, Electrical Engineering
181
Skills:
Semiconductors
Design
Storage
Gennady Feygin Photo 2

Gennady Feygin

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Gennady Feygin Photo 3

Gennady Feygin

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Friends:
Alla Gubenko, Oren Eliezer, Anna Mordukhovich, Ellie Feygin, Jeff Kerr

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