Gary M Hurtz

age ~54

from San Francisco, CA

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Also known as:

Gary Michael Hurtz
Gary Hurt

Connected to:

Gary Hurtz Phones & Addresses

San Francisco, CA
1339 Calle De Las Granvas, Livermore, CA 94551 • 925-449-3344
2705 Fressia Ct, Pleasanton, CA 94588
Dublin, CA
Hayward, CA
Alameda, CA
Allen, TX

Work

Company:

Pakal technologies, inc
Jul 2019
Position:

Executive vice president of applications, marketing, and sales

Education

Degree:

Masters, Master of Science In Electrical Engineering
School / High School:

Uc Santa Barbara
1994 to 1995
Specialities:

Electrical Engineering

Skills

Power Management • Semiconductors • Ic • Semiconductor Industry • Analog • Mixed Signal • Electronics • Asic • Product Management • Cross Functional Team Leadership • Analog Circuit Design • Product Marketing • Consumer Electronics • Engineering Management • Product Development • Power Electronics • Product Engineering • Cmos • Competitive Analysis • Start Ups • Strategy • Embedded Systems • New Business Development • Silicon • Wireless • Marketing Strategy • Strategic Planning • Business Strategy • Business Development • Engineering • Program Management • Analog Design • Semiconductor Manufacturing • P&L Management • Microelectronics • Strategy Development • Team Leadership • Cost Reduction • Management

Languages

English

Industries

Semiconductors

Name / Title

Company / Classification

Phones & Addresses

Gary Hurtz
Sales And Marketing Executive, Marketing Director

Analog Devices, Inc
Mfg Semiconductors/Related Devices · Semiconductor and Related Device Manufacturing

3550 N 1 St, San Jose, CA 95134
408-382-3280, 408-383-9512, 408-382-3000, 408-727-9222

Resumes

Co-Founder And Chief Technology Officer

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Location:

680 Mission St, San Francisco, CA 94105

Industry:

Semiconductors

Work:

Pakal Technologies, Inc
Executive Vice President of Applications, Marketing, and Sales
Pakal Technologies, Inc
Vice President Applications and Marketing
Stellour Group Corporation
Co-Founder and Chief Technology Officer
Enovix Corp. Jun 2012 - Sep 2015
Senior Director Applications and Technical Marketing
Active Semiconductors Inc Mar 2006 - Jun 2011
Vice President, Power Management Technology

Education:

Uc Santa Barbara 1994 - 1995
Masters, Master of Science In Electrical Engineering, Electrical Engineering Uc Santa Barbara 1990 - 1994
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering

Skills:

Power Management
Semiconductors
Ic
Semiconductor Industry
Analog
Mixed Signal
Electronics
Asic
Product Management
Cross Functional Team Leadership
Analog Circuit Design
Product Marketing
Consumer Electronics
Engineering Management
Product Development
Power Electronics
Product Engineering
Cmos
Competitive Analysis
Start Ups
Strategy
Embedded Systems
New Business Development
Silicon
Wireless
Marketing Strategy
Strategic Planning
Business Strategy
Business Development
Engineering
Program Management
Analog Design
Semiconductor Manufacturing
P&L Management
Microelectronics
Strategy Development
Team Leadership
Cost Reduction
Management

Languages:

English

Us Patents

Current Source Methods And Apparatus For Light Emitting Diodes
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US Patent:

6538394, Mar 25, 2003
Filed:

Mar 30, 2001
Appl. No.:

09/822620
Inventors:

Karl Richard Volk - Scotts Valley CA
Andrew J. Mrizek - San Jose CA
Gary Hurtz - Pleasanton CA
Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA
International Classification:

G05F 100
US Classification:

315291, 315307, 362800
Abstract:

Current source methods and apparatus for light emitting diodes providing constant diode current and illumination in the presence of voltage and process variations. The method comprises providing a predetermined current through a first transistor, and mirroring the current through the first transistor to at least one additional transistor while holding the voltage across the first transistor to a predetermined value, wherein each additional transistor is coupled in series with a light emitting diode. An exemplary circuit, as well as various illustrative applications are disclosed.

Power Device Having Reduced Reverse Bias Leakage Current
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US Patent:

6979861, Dec 27, 2005
Filed:

May 30, 2002
Appl. No.:

10/159558
Inventors:

Vladimir Rodov - Redondo Beach CA, US
Paul Chang - Saratoga CA, US
Gary M. Hurtz - Pleasanton CA, US
Geeng-Chuan Chern - Cupertino CA, US
Jianren Bao - Fullerton CA, US
Assignee:

APD Semiconductor, Inc. - San Jose CA
International Classification:

H01L029/76
H01L029/94
H01L031/062
H01L031/113
H01L031/119
US Classification:

257329, 257471, 438212
Abstract:

A power device having vertical current flow through a semiconductor body of one conductivity type from a top electrode to a bottom electrode includes at least one gate electrode overlying a gate insulator on a first surface of the body, a channel region of second conductivity type in the surface of the body underlying all of the gate electrode, a first doped region of the second conductivity type contiguous with the channel region and positioned deeper in the body than the channel region and under a peripheral region of the gate electrode, and a second doped source/drain region in the surface of the body abutting the channel region and adjacent to the gate electrode. When the gate is forward biased, an inversion region extends through the channel region and electrically connects the first electrode and the second electrode with a small Vnear to the area between adjacent P bodies being flooded with electrons and denuded of holes. Therefore, at any forward bias this area conducts as an N-type region. When the gate electrode is reverse biased, the long channel region underlying the full length of the gate electrode reduces reverse leakage current.

Programmable Analog Tile Programming Tool
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US Patent:

8079007, Dec 13, 2011
Filed:

Jan 30, 2009
Appl. No.:

12/322374
Inventors:

Steven Huynh - Fremont CA, US
Matthew A. Grant - Palo Alto CA, US
Gary M. Hurtz - Pleasanton CA, US
David J. Kunst - Cupertino CA, US
Trey A. Roessig - Palo Alto CA, US
Assignee:

Active-Semi, Inc.
International Classification:

G06F 17/50
US Classification:

716120, 716118, 716127
Abstract:

A programmable analog tile integrated circuit programming tool communicates a power management control characteristic query soliciting control requirement information for a novel power management integrated circuit (PMIC) tile in a multi-tile power management integrated circuit (MTPMIC). The programming tool receives a user response to the query indicating control requirements across a network. The novel PMIC tiles have a pre-defined physical structure including all memory structures required for configuration of each tile and a bus portion. When combined in a multi-tile power management integrated circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. The memory structure of each tile is individually addressable via the standardized bus. Thus, in response to control requirements, the programming tool programs a PMIC tile that is part of a MTPMIC to meet the control requirements.

Analog Tile Selection, Placement, Configuration And Programming Tool
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US Patent:

8219956, Jul 10, 2012
Filed:

Jan 30, 2009
Appl. No.:

12/322400
Inventors:

Steven Huynh - Fremont CA, US
Matthew A. Grant - Palo Alto CA, US
Gary M. Hurtz - Pleasanton CA, US
David J. Kunst - Cupertino CA, US
Trey A. Roessig - Palo Alto CA, US
Assignee:

Active-Semi, Inc.
International Classification:

G06F 17/50
US Classification:

716119, 716120
Abstract:

An Analog Tile Selection, Placement, Configuration and Programming (ATSPCP) tool communicates a power management characteristic query over a network. The query is displayed to a user on a webpage. The query is a solicitation for desired characteristics of a Power Management Integrated Circuit (PMIC). After receiving user requirements in a response to the query, the tool selects a number of power management integrated circuit tiles having pre-defined physical structures. The pre-defined structure of each tile includes a bus portion and a memory structure for storing configuring information for the tile. When combined in a Multi-Tile Power Management Integrated Circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC that meets the user requirements. The ATSPCP tool combines the physical layout data of each selected PMIC tile to form composite physical layout data for the overall MTPMIC.

Programmable Analog Tile Placement Tool
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US Patent:

8225260, Jul 17, 2012
Filed:

Jan 30, 2009
Appl. No.:

12/322376
Inventors:

Steven Huynh - Fremont CA, US
Matthew A. Grant - Palo Alto CA, US
Gary M. Hurtz - Pleasanton CA, US
David J. Kunst - Cupertino CA, US
Trey A. Roessig - Palo Alto CA, US
Assignee:

Active-Semi, Inc.
International Classification:

G06F 17/50
US Classification:

716118, 716116, 716119, 716121, 716124, 716125, 716132, 716135, 716139
Abstract:

A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC.

Programmable Analog Tile Configuration Tool
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US Patent:

8341582, Dec 25, 2012
Filed:

Jan 30, 2009
Appl. No.:

12/322373
Inventors:

Steven Huynh - Fremont CA, US
Matthew A. Grant - Palo Alto CA, US
Gary M. Hurtz - Pleasanton CA, US
David J. Kunst - Cupertino CA, US
Trey A. Roessig - Palo Alto CA, US
Assignee:

Active-Semi, Inc.
International Classification:

G06F 17/50
US Classification:

716120, 716102, 716116, 716119, 716121, 716139, 707769
Abstract:

A programmable analog tile integrated circuit configuration tool communicates a power management control characteristic query soliciting control requirement information for a novel Power Management Integrated Circuit (PMIC) tile in a Multi-Tile Power Management Integrated Circuit (MTPMIC). The configuration tool receives a user response to the query indicating control requirements across a network. The PMIC tile includes configuration registers. Configuration information bit values stored in the configuration registers control the operational characteristics of the functional circuitry of the tile. The configuration registers of each novel PMIC tile are accessible at pre-defined addresses on a standardized bus of the MTPMIC. In response to the user response, the configuration tool generates appropriate tile configuration information for loading the configuration registers such that the PMIC tile within the MTPMIC is programmed to satisfy the user's control requirements.

Communicating Configuration Information Across A Programmable Analog Tile To Another Tile
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US Patent:

20100199247, Aug 5, 2010
Filed:

Jan 30, 2009
Appl. No.:

12/322375
Inventors:

Steven Huynh - Fremont CA, US
Matthew A. Grant - Palo Alto CA, US
Gary M. Hurtz - Pleasanton CA, US
David J. Kunst - Cupertino CA, US
Trey A. Roessig - Palo Alto CA, US
International Classification:

G06F 17/50
US Classification:

716 8
Abstract:

A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.

Power Device Having Vertical Current Path With Enhanced Pinch-Off For Current Limiting
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US Patent:

6515330, Feb 4, 2003
Filed:

Jan 2, 2002
Appl. No.:

10/037495
Inventors:

Gary M. Hurtz - Pleasanton CA
Vladimir Rodov - Redondo Beach CA
Geeng-Chuan Chern - Cupertino CA
Paul Chang - Saratoga CA
Assignee:

APD Semiconductor, Inc. - San Jose CA
International Classification:

H01L 2976
US Classification:

257328, 257341
Abstract:

A semiconductor current limiting device is provided by a two-terminal vertical N(P)-channel MOSFET device having the gate, body, and source terminals tied together as the anode and the drain terminal as the cathode. The doping profile of the body is so tailored with ion implantation that a depletion region pinches off to limit current. The body comprises a shallow implant to form a MOS channel and an additional deep implant through a spacer shielding the channel area. Implanted a higher energies and at an acute angle, the deep implant protrudes into the regular current path of the vertical MOSFET.