Fadi Y Busaba

US Patent:

6369725, Apr 9, 2002

Filed:

Sep 26, 2000

Appl. No.:

09/669226

Inventors:

Fadi Y. Busaba - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 704

US Classification:

341 84, 708211

Abstract:

An exemplary embodiment of the invention is a method and system for converting a number from binary to decimal. The method includes obtaining an N-bit binary number and then determining the number of multiplications necessary to complete the conversion process by first determining the number of leading zeroes. The method then divides the N-bit number into 12-bit segments where each segment is represented as a binary coded decimal number. The method then multiplies at least one binary coded decimal number by a variable in response to the number of multiplications to determine the resulting decimal value.

US Patent:

6944753, Sep 13, 2005

Filed:

Apr 11, 2001

Appl. No.:

09/832544

Inventors:

Fadi Y. Busaba - Poughkeepsie NY, US
Christopher A. Krygowski - Lagrangeville NY, US
Wen H. Li - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F007/00

US Classification:

712224, 712221

Abstract:

A method for allowing a partial instruction to be executed in a fixed point unit pipeline during the instruction dispatch cycle creates a mask used to select which bits of the operands participate in a future logical operation of the fixed point unit back a cycle to the instruction dispatch stage of the fixed point unit. As an S/390 System improvement applicable to other computers, the mask is determined and created two cycles ahead of execution, or two cycles before the mask is actually used. Also, in the method used for moving the mask generation back by one cycle, mask generation overlaps the dispatch stage in the I-unit, and this provides a handshake between the I-unit and E-unit of the fixed point unit of the central processor unit of the computer system. The control setting selection process occurs in a predetermination cycle stage or e-1 (em1) stage for the mask generation and the register file read address. Speculative handshaking allows the E-1 stage to be created with no impact to the last stage of the I-Unit, such that no additional logic is needed and cycle time is not jeopardized.

US Patent:

7010676, Mar 7, 2006

Filed:

May 12, 2003

Appl. No.:

10/436296

Inventors:

Fadi Y. Busaba - Poughkeepsie NY, US
Klaus J. Getzlaff - Schoenaich, DE
Christopher A. Krygowski - Lagrangeville NY, US
Timothy J. Slegel - Staatsburg NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/38

US Classification:

712239, 712241

Abstract:

An embodiment of the invention is a processor for processing loop branch instructions. The processor includes an instruction unit for fetching and decoding instructions including at least one loop branch instruction. A branch prediction unit predicts target instructions to be fetched and decoded by the instruction unit in response to the loop branch instruction. An execution unit executes instructions from the instruction unit and maintains a counter indicating an iteration of a loop. The execution unit includes detection logic for detecting when the counter equals a threshold and notifies the branch prediction unit when the counter equals the threshold.

US Patent:

7082517, Jul 25, 2006

Filed:

May 12, 2003

Appl. No.:

10/435806

Inventors:

Fadi Y. Busaba - Poughkeepsie NY, US
Klaus J. Getzlaff - Schoenaich, DE
Christopher A. Krygowski - Lagrangeville NY, US
Timothy J. Slegel - Staatsburg NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30
G06F 15/00

US Classification:

712214

Abstract:

In a computer system for use as a symetrical multiprocessor, a superscalar microprocessor apparatus allows dispatching and executing multi-cycle and complex instructions Some control signals are generated in the dispatch unit and dispatched with the instruction to the Fixed Point Unit (FXU). Multiple execution pipes correspond to the instruction dispatch ports and the execution unit is a Fixed Point Unit (FXU) which contains three execution dataflow pipes (X, Y and Z) and one control pipe (R). The FXU logic then execute these instructions on the available FXU pipes. This results in optimum performance with little or no other complications. The presented technique places the flexibility of how these instructions will be executed in the FXU, where the actual execution takes place, instead of in the instruction decode or dispatch units or cracking by the compiler.

US Patent:

7085917, Aug 1, 2006

Filed:

May 12, 2003

Appl. No.:

10/435983

Inventors:

Fadi Y. Busaba - Poughkeepsie NY, US
Steven R. Carlough - Poughkeepsie NY, US
Christopher A. Krygowski - Lagrangeville NY, US
Timothy J. Slegel - Staatsburg NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30
G06F 15/00

US Classification:

712214

Abstract:

In a computer system, a method and apparatus for dispatching and executing multi-cycle and complex instructions. The method results in maximum performance for such without impacting other areas in the processor such as decode, grouping or dispatch units. This invention allows multi-cycle and complex instructions to be dispatched to one port but executed in multiple execution pipes without cracking the instruction and without limiting it to a single execution pipe. Some control signals are generated in the dispatch unit and dispatched with the instruction to the Fixed Point Unit (FXU). The FXU logic then execute these instructions on the available FXU pipes. This method results in optimum performance with little or no other complications. The presented technique places the flexibility of how these instructions will be executed in the FXU, where the actual execution takes place, instead of in the instruction decode or dispatch units or cracking by the compiler.

US Patent:

7149767, Dec 12, 2006

Filed:

May 12, 2003

Appl. No.:

10/436322

Inventors:

Fadi Y. Busaba - Poughkeepsie NY, US
Steven R. Carlough - Poughkeepsie NY, US
Christopher A. Krygowski - Lagrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/535

US Classification:

708651, 708656

Abstract:

A method of decimal division in a superscalar processor comprising: obtaining a first operand and a second operand; establishing a dividend and a divisor from the first operand and the second operand; determining a quotient digit and a resulting partial remainder; based on multiple parallel/simultaneous subtractions of at least one of the divisor and a multiple of the divisor from the dividend, utilizing dataflow elements of multiple execution pipes of the superscalar processor.

US Patent:

7167889, Jan 23, 2007

Filed:

May 12, 2003

Appl. No.:

10/436392

Inventors:

Fadi Y. Busaba - Poughkeepsie NY, US
Steven R. Carlough - Poughkeepsie NY, US
Christopher A. Krygowski - Lagrangeville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/523

US Classification:

708623

Abstract:

A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partial product term every two cycles. The partial product terms are created from the effective multiplicand and multiples of the multiplier, where the effective multiplicand is stored in a first register file, the multiples being ones times the effective multiplier, two times the effective multiplier, four times the effective multiplier and eight times the effective multiplier and the partial product terms are added to an accumulation of previous partial product terms shifted one digit right such that a digit shifted off is preserved as a result digit.

US Patent:

7167968, Jan 23, 2007

Filed:

Apr 29, 2004

Appl. No.:

10/834637

Inventors:

Fadi Y. Busaba - Poughkeepsie NY, US
Steven R. Carlough - Poughkeepsie NY, US
Mark A. Check - Hopewell Junction NY, US
Christopher A. Krygowski - Lagrangeville NY, US
Frank Tanzi - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/06

US Classification:

711201

Abstract:

A method of pre-aligning data for storage during instruction execution improves performance by eliminating the cycles otherwise required for data alignment. The method can convert data between ASCII and Packed Decimal format, and between Unicode Basic Latin and Packed Decimal format. Conversion to Packed Decimal format is needed for decimal hardware in a microprocessor designed to generate decimal results. Converting from Packed Decimal to ASCII and Unicode Basic Latin is necessary to report Decimal Arithmetic results in a required format for the application program. To further improve performance, all available write ports in the fixed point unit (FXU) are utilized to reduce the number of cycles necessary to store results. To prevent data fetching of the unused destination data from slowing down instruction execution, the destination locations are tested for storage access exceptions, but the data for these operands are not actually fetched. A single read request from the FXU to the operand buffers effectively reads the entire destination address (up to 8 double-words of data) in a single cycle.