Search

Fadi Y Busaba

age ~55

from Poughkeepsie, NY

Also known as:
  • Fadi Yusuf Busaba
  • Fadi Busaba
  • Fadi Yusuf Saba
  • Fadi Yusuf Bu
  • Fadi Saba
45 Beechwood Ave, Poughkeepsie, NY 12601

Fadi Busaba Phones & Addresses

  • 45 Beechwood Ave, Poughkeepsie, NY 12601
  • Greensboro, NC
  • Chestnut Hill, MA
  • Watertown, MA
  • Raleigh, NC
  • 45 Beechwood Park, Poughkeepsie, NY 12601

Us Patents

  • Method For Binary To Decimal Conversion

    view source
  • US Patent:
    6369725, Apr 9, 2002
  • Filed:
    Sep 26, 2000
  • Appl. No.:
    09/669226
  • Inventors:
    Fadi Y. Busaba - Poughkeepsie NY
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H03M 704
  • US Classification:
    341 84, 708211
  • Abstract:
    An exemplary embodiment of the invention is a method and system for converting a number from binary to decimal. The method includes obtaining an N-bit binary number and then determining the number of multiplications necessary to complete the conversion process by first determining the number of leading zeroes. The method then divides the N-bit number into 12-bit segments where each segment is represented as a binary coded decimal number. The method then multiplies at least one binary coded decimal number by a variable in response to the number of multiplications to determine the resulting decimal value.
  • Program Status Word Dependency Handling In An Out Of Order Microprocessor Design

    view source
  • US Patent:
    2011032, Dec 29, 2011
  • Filed:
    Jun 24, 2010
  • Appl. No.:
    12/822974
  • Inventors:
    Gregory W. Alexander - Pflugerville TX,
    Brian D. Barrick - Pflugerville TX,
    Michael Billeci - Poughkeepsie NY,
    Fadi Y. Busaba - Poughkeepsie NY,
    Bruce C. Giamei - Poughkeepsie NY,
    David A. Schroter - Round Rock TX,
  • Assignee:
    INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
  • International Classification:
    G06F 9/318
  • US Classification:
    712226, 712E09035
  • Abstract:
    A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.
  • Supporting Partial Recycle In A Pipelined Microprocessor

    view source
  • US Patent:
    8516228, Aug 20, 2013
  • Filed:
    Mar 19, 2008
  • Appl. No.:
    12/051486
  • Inventors:
    Khary J. Alexander - Poughkeepsie NY,
    Michael Billeci - Tivoli NY,
    Fadi Y. Busaba - Poughkeepsie NY,
    Bruce C. Giamei - Poughkeepsie NY,
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G06F 9/00
  • US Classification:
    712218, 712219
  • Abstract:
    A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.
  • Cracking Destructively Overlapping Operands In Variable Length Instructions

    view source
  • US Patent:
    8645669, Feb 4, 2014
  • Filed:
    May 5, 2010
  • Appl. No.:
    12/774299
  • Inventors:
    Khary J. Alexander - Poughkeepsie NY,
    Fadi Busaba - Poughkeepsie NY,
    Brian Curran - Saugerties NY,
    Bruce Giamei - Poughkeepsie NY,
    Christian Jacobi - Poughkeepsie NY,
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G06F 9/30
  • US Classification:
    712210
  • Abstract:
    A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The first set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical.
  • Operand Forwarding In A Superscalar Processor

    view source
  • US Patent:
    2004013, Jul 15, 2004
  • Filed:
    Jan 14, 2003
  • Appl. No.:
    10/341900
  • Inventors:
    Fadi Busaba - Poughkeepsie NY,
    Klaus Getzlaff - Schoenaich,
    Bruce Giamei - Poughkeepsie NY,
    Christopher Krygowski - Lagrangeville NY,
    Timothy Slegel - Staatsburg NY,
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G06F009/30
  • US Classification:
    712/218000
  • Abstract:
    A method and mechanism for improving Instruction Level Parallelism (ILP) of a program and eventually improving Instructions per cycle (IPC) allows dependent instructions to be grouped and dispatched simultaneously by forwarding the oldest instruction, or source instruction, General Register (GR) data to the other dependent instructions. A source instruction of a load type loading a GR value into a GR. The dependent instructions will then select the forwarded data to perform their computation. The dependent instructions use the same GR read address as the source instruction. Another source instruction of a load type loads a memory data into a GR. The loaded memory data is forwarded or replicated on the memory read bus of the other dependent instructions. The mechanism allows Address Generator Output to be forwarded to the other dependent instructions when the source instruction is a load type loading a memory address into a GR. Then the loaded address is forwarded or replicated on the address bus of the other dependent instructions. Then, also, Control Register (CR) data is forwarded to the other dependent instructions when the source instruction is a load type loading a CR value into a General Register. Then the loaded CR data is forwarded or replicated on the CR data bus of other dependent instructions. When the source instruction is a load type loading an immediate value into a General Register, loaded immediate data is forwarded or replicated on the immediate data bus of other dependent instructions.
  • Result Forwarding In A Superscalar Processor

    view source
  • US Patent:
    2004013, Jul 15, 2004
  • Filed:
    Jan 14, 2003
  • Appl. No.:
    10/341995
  • Inventors:
    Fadi Busaba - Poughkeepsie NY,
    Klaus Getzlaff - Schoenaich,
    Bruce Giamei - Poughkeepsie NY,
    Christopher Krygowski - Lagrangeville NY,
    Timothy Slegel - Staatsburg NY,
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G06F009/30
  • US Classification:
    712/218000
  • Abstract:
    A method and mechanism for improving Instruction Level Parallelism (ILP) of a program and eventually improving Instructions per cycle (IPC) allows dependent instructions to be grouped and dispatched simultaneously by forwarding the oldest instruction, or source instruction, result to the other dependent instructions result buses or registers thus bypassing the dependent instruction execution stage. A source instruction that performs arithmetic, logical or rotate/shift type operation on operands and updates a GR with the computed result. A load type dependent or target instruction loading a GR value into a GR will then select the forwarded result of the source instruction to its write bus for the GR update. Another target instruction of a store type stores a memory data from a GR data. The result of source instruction is also used by the dependent instruction to update storage. The mechanism allows also the dependent instruction to be a load type that loads a GR data into a Control Register (CR). The result data of the source instruction is then selected by the target instruction for the CR update.
  • Computer System Method For A One Cycle Implementation Of Test Under Mask Instructions

    view source
  • US Patent:
    2004023, Nov 18, 2004
  • Filed:
    May 12, 2003
  • Appl. No.:
    10/436211
  • Inventors:
    Fadi Busaba - Poughkeepsie NY,
    Steven Carlough - Poughkeepsie NY,
    Christopher Krygowski - Lagrangeville NY,
    Wen Li - Poughkeepsie NY,
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G06F007/38
  • US Classification:
    708/233000
  • Abstract:
    In a computer system, a method for executing a Test under Mask instruction in the Fixed Execution Unit (FXU) allows for the execution of these instructions in just one cycle single execution cycle inside the FXU without adding any dedicated data flow circuitry by giving the highest priority to the leftmost selected bit in the operand. The preferred method breaks the execution of each instruction into four different micro-operations that can be executed in parallel in one CPU cycle, and during the E0 cycle of these instructions, data from a first operand and from the Test under Mask instruction are loaded into the two working registers, an A-reg and a B-reg, and then, during the E1 dispatch cycle, the A-reg is rotated by the amount of 32-bits to align the bits of the mask with the corresponding bits of the first operand, and during the same E1 dispatch cycle micro-operations are executed in the Fixed Execution Unit (FXU) giving the highest priority to the leftmost selected bit in the operand and the outcome of these micro-operations is used to calculate the condition code (CC) to implement the Test under Mask as a one-cycle implementation for test under mask instructions and the results of the execution sets the condition code.
  • Computer Instructions For Optimum Performance Of C-Language String Functions

    view source
  • US Patent:
    2004023, Nov 18, 2004
  • Filed:
    May 12, 2003
  • Appl. No.:
    10/435987
  • Inventors:
    Timothy Slegel - Staatsburg NY,
    Fadi Busaba - Poughkeepsie NY,
    Christopher Krygowski - Lagrangeville NY,
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G06F009/44
  • US Classification:
    712/223000
  • Abstract:
    Several new computer instructions are shown which are used to improve the performance of C or C++ language string functions. The instruction simultaneously compare multiple byte in two registers with each other and with all zeros and indicates the results of the comparison in the condition code and in a register which indicates the leftmost byte that compared or miscompared. The instructions may be exposed at the computer system's instruction set level, or it may be used internally by microcode running on the computer.

Facebook

Fadi Busaba Photo 1

Fadi Busaba

view source

Get Report for Fadi Y Busaba from Poughkeepsie, NY, age ~55
Control profile