Ernest W Balch

US Patent:

6396153, May 28, 2002

Filed:

Jan 25, 2001

Appl. No.:

09/768598

Inventors:

Raymond Albert Fillion - Niskayuna NY
Ernest Wayne Balch - Ballston Spa NY
Ronald Frank Kolc - Cherry Hill NJ
Robert John Wojnarowski - Ballston Lake NY
Leonard Richard Douglas - Burnt Hills NY
Thomas Bert Gorczyca - Schenectady NY

Assignee:

General Electric Company - Schenectady NY

International Classification:

H01L 2348

US Classification:

257774, 257773

Abstract:

One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.

US Patent:

6410356, Jun 25, 2002

Filed:

Mar 7, 2000

Appl. No.:

09/520751

Inventors:

Robert John Wojnarowski - Ballston Lake NY
Ernest Wayne Balch - Ballston Spa NY
Leonard Richard Douglas - Burnt Hills NY

Assignee:

General Electric Company - Schenectady NY

International Classification:

H01L 2166

US Classification:

438 15, 438 14, 438 17, 438125, 438126, 438411, 438619, 438623

Abstract:

A method for interconnecting high-temperature silicon carbide (SiC) devices enables such high-temperature devices to be used in fabricating electronic circuits of significant scale. This method comprises empirically measuring operational characteristics of a plurality of the devices to be interconnected, the operational characteristics comprising devices which are measured to be non-working and devices which are measured to be working; characterizing the operational characteristics in an operational characteristics map; designing interconnection paths between and among the devices that are characterized to be working by the operational characteristics map; and excluding from the interconnection paths, devices that are characterized to be non-working by the operational characteristics map. A preferred embodiment of this method further includes disposing a temporary polymer layer over the devices; forming via holes through the temporary polymer layer, to bonding pads of the devices; applying a current-balancing resistive metal over the temporary polymer layer; establishing connections between the current-balancing resistive metal and the bonding pads; designing the interconnection paths between and among the working devices by patterning the current-balancing resistive metal based on the operational characteristics map; and removing the temporary polymer layer.

US Patent:

6417062, Jul 9, 2002

Filed:

May 1, 2000

Appl. No.:

09/562194

Inventors:

Donald Franklin Foust - Glenville NY
James Wilson Rose - Guilderland NY
Ernest Wayne Balch - Ballston Spa NY

Assignee:

General Electric Company - Niskayuna NY

International Classification:

H01L 2120

US Classification:

438384, 438382, 438686, 438785, 427534

Abstract:

A method of forming a ruthenium dioxide film for such purposes as the fabrication of stable thin-film resistors for microcircuits. The method generally entails forming an inorganic ruthenium-based film on a substrate, and then thermally decomposing at least a portion of the ruthenium-based film by exposure to a high-intensity beam of radiation, preferably visible light, to yield a ruthenium dioxide film on the substrate. Particular ruthenium-based precursors useful for forming the ruthenium-based film include ruthenium (III) chloride (RuCl. nH O) and ruthenium (III) nitrosyl nitrate. The method does not require a thermal treatment that heats the bulk of the substrate on which the ruthenium dioxide film is formed, and is therefore suitable for non-ceramic substrate materials, e. g. , polymers such as those used as printed circuit boards (PCBs) and flexible circuits.

US Patent:

6602739, Aug 5, 2003

Filed:

Mar 19, 2002

Appl. No.:

10/101231

Inventors:

James Wilson Rose - Guilderland NY
Thomas Bert Gorczyca - Schenectady NY
Christopher James Kapusta - Duanesburg NY
Ernest Wayne Balch - Ballston Spa NY
Kevin Matthew Durocher - Waterford NY

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H01L 2144

US Classification:

438126, 438106, 438109, 438125

Abstract:

A method for making a multichip âHDIâ module includes the step of making a substrate for supporting the semiconductor or solid-state chips (or other components) by applying electrical conductor in a pattern to a first dielectric sheet, and applying encapsulating material to the electrical conductor. Apertures are made in the first dielectric sheet and encapsulant at locations at which the chips (or other components) are to be located. The components are affixed to a second dielectric sheet at locations registered with the apertures in the first sheet, and the sheets are juxtaposed with the chips extending into the apertures. This results in the formation of gaps between the components and the edges of the apertures, which gaps are then filled with hardenable or curable material. Electrical connection is made to the pads of the chips by means of a multilayer structure of dielectric sheets with conductor patterns, interconnected by means of plated-through vias.

US Patent:

6603145, Aug 5, 2003

Filed:

May 2, 2002

Appl. No.:

10/136626

Inventors:

Robert John Wojnarowski - Ballston Lake NY
Ernest Wayne Balch - Ballston Spa NY
Leonard Richard Douglas - Burnt Hills NY

Assignee:

General Electric Company - Niskayuna NY

International Classification:

H01L 310312

US Classification:

257 77, 257744, 257773

Abstract:

A method for interconnecting high-temperature silicon carbide (SiC) devices enables such high-temperature devices to be used in fabricating electronic circuits of significant scale. This method comprises empirically measuring operational characteristics of a plurality of the devices to be interconnected, the operational characteristics comprising devices which are measured to be non-working and devices which are measured to be working; characterizing the operational characteristics in an operational characteristics map; designing interconnection paths between and among the devices that are characterized to be working by the operational characteristics map; and excluding from the interconnection paths, devices that are characterized to be non-working by the operational characteristics map. A preferred embodiment of this method further includes disposing a temporary polymer layer over the devices; forming via holes through the temporary polymer layer, to bonding pads of the devices; applying a current-balancing resistive metal over the temporary polymer layer; establishing connections between the current-balancing resistive metal and the bonding pads; designing the interconnection paths between and among the working devices by patterning the current-balancing resistive metal based on the operational characteristics map; and removing the temporary polymer layer.

US Patent:

6614103, Sep 2, 2003

Filed:

Sep 1, 2000

Appl. No.:

09/654163

Inventors:

Kevin Matthew Durocher - Waterford NY
Ernest Wayne Balch - Ballston NY
Vikram B. Krishnamurthy - Clifton Park NY
Richard Joseph Saia - Niskayuna NY
Herbert Stanley Cole - Burnt Hills NY
Ronald Frank Kolc - Cherry Hill NJ

Assignee:

General Electric Company - Schenectady NY

International Classification:

B60Q 100

US Classification:

257678, 257291, 257292, 257293, 257103, 257 99, 257 75, 257 88, 257725, 257728, 257432, 257431, 257433, 257434, 257712, 313486, 313489, 313483, 313 12, 313113, 313114, 362 31, 362240, 362294, 362373, 362494, 362800

Abstract:

There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.

US Patent:

6730533, May 4, 2004

Filed:

Mar 14, 2003

Appl. No.:

10/387862

Inventors:

Kevin Matthew Durocher - Waterford NY
Ernest Wayne Balch - Ballston NY
Vikram B. Krishnamurthy - Clifton Park NY
Richard Joseph Saia - Niskayuna NY
Herbert Stanley Cole - Burnt Hills NY
Ronald Frank Kolc - Cherry Hill NJ

Assignee:

General Electric Company - Schenectady NY

International Classification:

H01L 2100

US Classification:

438 26, 438106, 438118, 438119, 438125, 438126

Abstract:

There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.

US Patent:

6733711, May 11, 2004

Filed:

Mar 14, 2003

Appl. No.:

10/387835

Inventors:

Kevin Matthew Durocher - Waterford NY
Ernest Wayne Balch - Ballston NY
Vikram B. Krishnamurthy - Clifton Park NY
Richard Joseph Saia - Niskayuna NY
Herbert Stanley Cole - Burnt Hills NY
Ronald Frank Kolc - Cherry Hill NJ

Assignee:

General Electric Company - Schenectady NY

International Classification:

B29C 4514

US Classification:

26427214, 26427217, 26427215, 29846, 29854, 29855

Abstract:

There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.