Edem J Wornyo

US Patent:

20160064326, Mar 3, 2016

Filed:

Nov 10, 2015

Appl. No.:

14/937812

Inventors:

- Coppell TX, US
- Armonk NY, US
Lawrence A. Clevenger - LaGrangeville NY, US
Carl Radens - LaGrangeville NY, US
Edem Wornyo - Danbury CT, US

International Classification:

H01L 23/525
H01L 49/02
H01L 23/522

Abstract:

Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

US Patent:

20160020105, Jan 21, 2016

Filed:

Sep 30, 2015

Appl. No.:

14/871157

Inventors:

- Armonk NY, US
- Coppell TX, US
Richard S. Wise - Newburgh NY, US
Edem Wornyo - Danbury CT, US
Yiheng Xu - Hopewell Junction NY, US
John Zhang - Fishkill NY, US

International Classification:

H01L 21/28
H01L 21/3213

Abstract:

An ashing chemistry employing a combination of Cland Nis provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.

US Patent:

20150243510, Aug 27, 2015

Filed:

Feb 24, 2014

Appl. No.:

14/187598

Inventors:

- Coppell TX, US
- Armonk NY, US
Richard S. Wise - Newburgh NY, US
Edem Wornyo - Danbury CT, US
Yiheng Xu - Hopewell Junction NY, US
John Zhang - Fishkill NY, US

Assignee:

STMicroelectronics, Inc. - Coppell TX
International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/308

Abstract:

An ashing chemistry employing a combination of Cland Nis provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.

US Patent:

20150115401, Apr 30, 2015

Filed:

Oct 31, 2013

Appl. No.:

14/068198

Inventors:

- Armonk NY, US
- Coppell TX, US
Carl Radens - LaGrangeville NY, US
Yiheng Xu - Hopewell Junction NY, US
Edem Wornyo - Danbury CT, US

International Classification:

H01L 49/02
H01L 21/3105
H01L 21/02

US Classification:

257530, 438382, 438692

Abstract:

A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method of fabricating such a structure cleverly takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

US Patent:

20150002213, Jan 1, 2015

Filed:

Jun 28, 2013

Appl. No.:

13/931692

Inventors:

- Armonk NY, US
- Coppell TX, US
Carl Radens - LaGrangeville NY, US
Yiheng Xu - Hopewell Junction NY, US
Edem Wornyo - Danbury CT, US

International Classification:

H01L 23/525
H01F 17/02
H01L 49/02

US Classification:

327525, 336186, 438600

Abstract:

Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.