Douglas M Mckay

US Patent:

7382142, Jun 3, 2008

Filed:

May 18, 2005

Appl. No.:

11/133021

Inventors:

Fu Chiung Chong - Saratoga CA, US
Andrew Kao - Fremont CA, US
Douglas McKay - San Jose CA, US
Anna Litza - Cupertino CA, US
Douglas Modlin - Palo Alto CA, US
Sammy Mok - Cupertino CA, US
Nitin Parekh - Los Altos CA, US
Frank John Swiatowiec - San Jose CA, US
Zhaohui Shan - San Jose CA, US

Assignee:

NanoNexus, Inc. - San Jose CA

International Classification:

G01R 31/02

US Classification:

324754

Abstract:

An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.

US Patent:

7872482, Jan 18, 2011

Filed:

Sep 19, 2007

Appl. No.:

11/858064

Inventors:

Fu Chiung Chong - Saratoga CA, US
Andrew Kao - Fremont CA, US
Douglas McKay - San Jose CA, US
Anna Litza - Cupertino CA, US
Douglas Modlin - Palo Alto CA, US
Sammy Mok - Cupertino CA, US
Nitin Parekh - Los Altos CA, US
Frank John Swiatowiec - San Jose CA, US
Zhaohui Shan - Spring TX, US

Assignee:

Verigy (Singapore) Pte. Ltd - Singapore

International Classification:

G01R 31/02

US Classification:

324754

Abstract:

An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.

US Patent:

7884634, Feb 8, 2011

Filed:

Jan 15, 2009

Appl. No.:

12/354520

Inventors:

Fu Chiung Chong - Saratoga CA, US
Andrew Kao - Fremont CA, US
Douglas McKay - San Jose CA, US
Anna Litza - Cupertino CA, US
Douglas Modlin - Palo Alto CA, US
Sammy Mok - Cupertino CA, US
Nitin Parekh - Los Altos CA, US
Frank John Swiatowiec - San Jose CA, US
Zhaohui Shan - Spring TX, US

Assignee:

Verigy (Singapore) Pte, Ltd - Singapore

International Classification:

G01R 31/26

US Classification:

324765

Abstract:

An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.

US Patent:

20100026331, Feb 4, 2010

Filed:

Dec 4, 2007

Appl. No.:

12/517528

Inventors:

Fu Chiung Chong - Saratoga CA, US
Erh-Kong Chieh - Cupertino CA, US
Anna Litza - Cupertino CA, US
Douglas L. McKay - San Jose CA, US
Roman L. Milter - San Francisco CA, US
Sha Li - San Jose CA, US

International Classification:

G01R 31/02

US Classification:

324757

Abstract:

Enhanced microfabricated spring contact structures and associated methods, e.g. such as for electrical contactors and interposers, comprise improvements to spring structures that extend from the substrate surface, and/or improvements to structures on or within the support substrate. Improved spring structures and processes comprise embodiments having selectively formed and etched, coated and/or plated regions, which are optionally further processed through planarization and/or annealment. Enhanced solder connections and associated processes provide a gap between substrates for componentry, and or improved manufacturing techniques using distributed spacers. Enhanced probe card assembly structures and processes provide improved planarization adjustment and thermal stability.

US Patent:

20120023730, Feb 2, 2012

Filed:

Oct 5, 2011

Appl. No.:

13/253810

Inventors:

Fu Chiung CHONG - Saratoga CA, US
Erh-Kong CHIEH - Cupertino CA, US
Anna LITZA - Cupertino CA, US
Douglas L. McKAY - San Jose CA, US
Roman L. MILTER - San Francisco CA, US
Sha LI - San Jose CA, US

International Classification:

B23P 11/00

US Classification:

29428

Abstract:

Enhanced microfabricated spring contact structures and associated methods, e.g. such as for electrical contactors and interposers, comprise improvements to spring structures that extend from the substrate surface, and/or improvements to structures on or within the support substrate. Improved spring structures and processes comprise embodiments having selectively formed and etched, coated and/or plated regions, which are optionally further processed through planarization and/or annealment. Enhanced solder connections and associated processes provide a gap between substrates for componentry, and or improved manufacturing techniques using distributed spacers. Enhanced probe card assembly structures and processes provide improved planarization adjustment and thermal stability.