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Dion N Heisler

age ~58

from Colorado Springs, CO

Also known as:
  • Dion A Heisler
  • Dion H Heisler
  • Nickolas D Heisler
  • Dion N Heibler
  • Dion Klingensmith
  • Nickolas Heisler Dion
  • Heisler Dion
Phone and address:
2710 Fieldstone Rd, Colorado Springs, CO 80919
719-262-0344

Dion Heisler Phones & Addresses

  • 2710 Fieldstone Rd, Colorado Spgs, CO 80919 • 719-262-0344
  • 2415 Amberwood Ln, Colorado Springs, CO 80920 • 719-262-0344
  • Broomfield, CO
  • 2140 Widgeon Dr, Johnstown, CO 80534
  • The Dalles, OR
  • Altadena, CA
  • Devils Lake, ND
  • Weldona, CO
  • 2710 Fieldstone Rd, Colorado Springs, CO 80919

Work

  • Company:
    Rt logic
    Apr 2017 to May 2020
  • Position:
    Project manager

Education

  • Degree:
    Master of Business Administration, Masters
  • School / High School:
    University of Colorado Colorado Springs
    2002 to 2004
  • Specialities:
    Financial Management, Finance

Skills

Telecommunications • Engineering Management • Program Management • Wireless Technologies • Cross Functional Team Leadership • Product Management • Project Management • Leadership • Engineering • Product Development • Debugging • Testing • Agile Project Management • Scrum • Jira • Ip • Lte • Internet Protocol Suite • Software Development • Sip • Manufacturing • Ethernet • Embedded Systems • Linux • Tcp/Ip • Embedded Software • Integration • Wireless • Systems Engineering • Wireless Networking • Voip • Electronics • Software Engineering

Emails

d***r@aol.com

Industries

Telecommunications

Us Patents

  • Interface For Detection And Control Of Multiple Test Probes

    view source
  • US Patent:
    7339367, Mar 4, 2008
  • Filed:
    Apr 28, 2006
  • Appl. No.:
    11/413990
  • Inventors:
    Dion N. Heisler - Colorado Springs CO, US
    Nimal K. K. Gamage - Fort Collins CO, US
  • Assignee:
    Agilent Technologies, Inc. - Santa Clara CA
  • International Classification:
    G01R 1/38
  • US Classification:
    324115, 324 725, 324754
  • Abstract:
    An interface module. The interface module includes a probe identification module configured for connection to an identification bus, a probe detect module configured for connection to a detect-control bus, a power control module configured for connection to the detect-control bus, a control and data module configured for connection to a control-data bus, and multiple connectors. Each connector has an associated hot swap circuit. For each connector, if the probe detect module detects connection of that connector to a test probe via connection of that connector to the probe detect module, the probe identification module is configured to enable transfer of an identification label identifying that test probe to that test probe via that connector and the control and data module is configured to enable transfer of control instructions and data between the control-data bus and the test probe via connection of the control and data module to that connector.
  • Test Probe Having Modular Components

    view source
  • US Patent:
    7362091, Apr 22, 2008
  • Filed:
    Apr 28, 2006
  • Appl. No.:
    11/413836
  • Inventors:
    Dion N. Heisler - Colorado Springs CO, US
    Nimal K. K. Gamage - Fort Collins CO, US
  • Assignee:
    Agilent Technologies, Inc. - Santa Clara CA
  • International Classification:
    G01R 31/02
  • US Classification:
    3241581, 324754, 4551151
  • Abstract:
    A test probe. The test probe includes an interconnect module configured to connect to a modular, replaceable wireless module, a connect module configured to communicate with a communication network and the wireless module, an identification module configured to receive and transmit an identification of the test probe, an audio module configured to enable transfer of audio data from/for communication with the communication network from/to the wireless module and to translate audio data to/from audio signals, and a computer configured to enable transfer of audio signals from/to the audio module, transfer of digital data from/to the wireless module, and transfer of test data to/from a remote controller. Test data from the remote controller comprises instructions to control the wireless module and data for the wireless module to transfer to the connect module, and test data transmitted to the remote controller comprises digital data and audio data received from the wireless module.
  • Edram With Integrated Generation And Control Of Write Enable And Column Latch Signals And Method For Making Same

    view source
  • US Patent:
    58354425, Nov 10, 1998
  • Filed:
    Mar 22, 1996
  • Appl. No.:
    8/620450
  • Inventors:
    James Dean Joseph - Monument CO
    Dion Nickolas Heisler - Colorado Springs CO
    Doyle James Heisler - Colorado Springs CO
  • Assignee:
    Enhanced Memory Systems, Inc. - Colorado Springs CO
  • International Classification:
    G11C 800
  • US Classification:
    36523008
  • Abstract:
    An EDRAM device includes an EDRAM memory array on a semiconductor chip. A row enable signal generator and a column address latch signal generator are provided on the same semiconductor chip for generating row enable and column address latch signals for application to the EDRAM memory array.
  • Edram Having A Dynamically-Sized Cache Memory And Associated Method

    view source
  • US Patent:
    59833130, Nov 9, 1999
  • Filed:
    Apr 10, 1996
  • Appl. No.:
    8/630489
  • Inventors:
    Doyle James Heisler - Colorado Springs CO
    James Dean Joseph - Monument CO
    Dion Nickolas Heisler - Colorado Springs CO
  • Assignee:
    Ramtron International Corporation - Colorado Springs CO
  • International Classification:
    G06F 1200
    G06F 1206
    G06F 1300
  • US Classification:
    711105
  • Abstract:
    The method and apparatus of the current invention relates to an intelligent cache management system for servicing a main memory and a cache. The cache resources are allocated to segments of main memory rows based on a simple or complex allocation process. The complex allocation performs a predictive function allocating scarce resources based on the probability of future use. The apparatus comprises a main memory coupled by a steering unit to a cache. The steering unit controls where in cache a given main memory row segment will be placed. The operation of the steering unit is controlled by an intelligent cache allocation unit. The unit allocates new memory access requests cache locations which are least frequently utilized. Since a given row segment may be placed anywhere in a cache row, the allocation unit performs the additional function of adjusting the column portion of a memory access request to compensate for the placement of the requested segment in the cache. The allocation unit accepts as input hit or miss information from page segment comparators greater than or equal to in number the number of segments of cache.
  • Multibus Cached Memory System

    view source
  • US Patent:
    58025600, Sep 1, 1998
  • Filed:
    Aug 30, 1995
  • Appl. No.:
    8/521597
  • Inventors:
    James Dean Joseph - Monument CO
    Doyle James Heisler - Colorado Springs CO
    Dion Nickolas Heisler - Colorado Springs CO
  • Assignee:
    Ramton International Corporation - Colorado Springs CO
  • International Classification:
    G06F 1200
  • US Classification:
    711119
  • Abstract:
    A method and apparatus for use in computer systems utilizes a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circuit for implementing cache policy and arbitrating memory refresh cycles.

Resumes

Dion Heisler Photo 1

Engineering Development Manager

view source
Location:
Colorado Springs, CO
Industry:
Telecommunications
Work:
Rt Logic Apr 2017 - May 2020
Project Manager

Jdsu Apr 2017 - May 2020
Engineering Development Manager

Agilent Technologies Apr 2000 - Apr 2010
Hw Program Manager

Artesyn Technologies 1996 - 2000
Manufacturing Engineering Manager
Education:
University of Colorado Colorado Springs 2002 - 2004
Master of Business Administration, Masters, Financial Management, Finance
North Dakota State University
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Telecommunications
Engineering Management
Program Management
Wireless Technologies
Cross Functional Team Leadership
Product Management
Project Management
Leadership
Engineering
Product Development
Debugging
Testing
Agile Project Management
Scrum
Jira
Ip
Lte
Internet Protocol Suite
Software Development
Sip
Manufacturing
Ethernet
Embedded Systems
Linux
Tcp/Ip
Embedded Software
Integration
Wireless
Systems Engineering
Wireless Networking
Voip
Electronics
Software Engineering

Youtube

2008 HGA Masters Dion Heisler

The 8th annual HGA Masters was held on May 23, 2008 at Highlands Ranch...

  • Duration:
    2m 24s

Dion Heisler Wins all 3 Card Games

  • Duration:
    1m 20s

Interview with Dion and Kory before Round Two...

Exclusive interview with Dion Heisler and Kory Carpenter before Round ...

  • Duration:
    1m 26s

Dion Heisler wins Black Jack

I a crazy finish Dion wins Black Jack.

  • Duration:
    54s

Dion Hits 7 Out of Bounds.wmv

Dion Heisler struggles off the tee on hole number one and hits 7 out o...

  • Duration:
    1m 32s

Dion wins blitz at the 2010 HGA Phoenix Open

Dion Heisler wins Blitz by defeating Jamie Hoffner.

  • Duration:
    33s

Playing lessons by Dean Heisler

HGA Tour player Dean Heisler takes time to help Josh Hoffner with his ...

  • Duration:
    1m 59s

Dion & the Belmonts - A Teenager In Love (Mar...

Dion & the Belmonts made 8 appearances in the 3 seasons BeechNut was o...

  • Duration:
    2m 49s

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