Dennis A Ruffer

US Patent:

20090132792, May 21, 2009

Filed:

Nov 15, 2007

Appl. No.:

11/985566

Inventors:

Dennis Arthur Ruffer - Castle Rock CO, US

International Classification:

G06F 9/30

US Classification:

712220, 712E09016

Abstract:

The apparatus used includes a multi core computer processor where a plurality of processors is located on a single substrate Processors are connected to their nearest neighbor directly by single drop data busses The method is executed by an application code that includes functions which determine the internode timing. These functions are performed as the code executes. The code performs these functions by utilizing manually specified real time for clock cycles. In addition, captured data from an event driven simulator presents accurate clock cycle count information for the hardware. The code generates timing diagrams using this data. The timing diagrams can be used to compare and analyze the code behavior as it executes in the target multiprocessor array hardware. This method allows determination of how the actual hardware events correlate to the expected events that were simulated for a given instruction sequence.