Dean S Susnow

US Patent:

6594329, Jul 15, 2003

Filed:

Nov 1, 1999

Appl. No.:

09/432050

Inventors:

Dean S. Susnow - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 2500

US Classification:

375372, 710 57

Abstract:

An NGIO Elastic Buffer is provided for enabling link data received from an NGIO link to be synchronized into a receiver clock domain of a data receiver responsible for processing that data in a computer network. Such Elastic Buffer may comprise a memory coupled to receive link data from a data transmitter and to store the link data in a plurality of addressable memory locations; a write control mechanism which operates at a link clock for selecting as a write address the address of a memory location of the memory to store the link data, and for preventing an IDLE signal included in the link data from being stored in the memory so as to prohibit data overflow in the memory; and a read control mechanism which operates at a receiver clock for selecting as a read address the address of a memory location of the memory to retrieve the link data as receiver data, and for inserting No-Operation (NOP) sequences into the receiver data when the memory is determined empty so as to prohibit data underflow in the memory.

US Patent:

6606328, Aug 12, 2003

Filed:

Dec 15, 1999

Appl. No.:

09/461394

Inventors:

Dean Susnow - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04M 700

US Classification:

370465, 341 58

Abstract:

Look ahead encoder and decoder architecture. To increase the encoding speed, bytes of input data to be encoded are applied in parallel to each encoder of a pair of encoders in the look ahead encoder architecture. One encoder of each pair receives a first control input signal, while the other receives a second control input signal. The output bytes of binary data from the two encoders are applied to a multiplexer which selects the proper output byte based on the control output signal resulting from the immediately preceding encoded output byte of binary data. In one embodiment, a single encoder encodes the previous byte, doubling the encoding speed. In a second embodiment, a number of encoder pairs are utilized, with the multiplexers connected in a ring to utilize the selected control output signal from one multiplexer as the select signal for the next multiplexer in the ring, increasing the encoder speed by a factor equal to the number of encoder pairs. The look ahead decoder archtecture is correspondingly structured. Data communication systems incorporating such encoder and decoder architecture are provided.

US Patent:

6625768, Sep 23, 2003

Filed:

Mar 29, 2000

Appl. No.:

09/537398

Inventors:

Dean S. Susnow - Portland OR
Brian M. Collins - Aloha OR
Tom E. Burton - Vancouver WA
Dominic J. Gasbarro - Forest Grove OR
Brian M. Leitner - Hillsboro OR
Ni Jie - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 3128

US Classification:

714729

Abstract:

A test bus architecture for testing an integrated circuit having a plurality of agents includes providing both a test block select signal and test function select signal to a plurality of select decoders respectively disposed in each of the plurality of agents. The test block select signal has a number of states at least equal to the number of agents and the test function select signal at least equal to a maximum number of internal signal groups of any one of the agents, each select decoder having at least one internal signal group which is outputted from circuitry to be tested within the agent of the select decoder. An output from each of the select decoders is fed to a test bus output such that a selected internal signal group is outputted to the test bus output upon the agent of the selected signal group being selected by the state of the test block select signal and the selected signal group being selected by the state of the test function select signal by the select decoder.

US Patent:

6725388, Apr 20, 2004

Filed:

Jun 13, 2000

Appl. No.:

09/592670

Inventors:

Dean S. Susnow - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 112

US Classification:

713400

Abstract:

Commands are passed between first and second asynchronous clock domains. Unique coded command signals are inserted into a data stream transmitted from the first asynchronous clock domain to the second asynchronous clock domain. They are passed without change from the first asynchronous clock domain to the second asynchronous clock domain through an elastic buffer. The unique coded command signals are then decoded in receiver circuitry in the second asynchronous clock domain. Process circuitry in the second asynchronous clock domain is controlled according to the decoded command signals.

US Patent:

6741602, May 25, 2004

Filed:

Mar 30, 2000

Appl. No.:

09/538263

Inventors:

Dean S. Susnow - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 1228

US Classification:

370412, 370419, 370413, 370465

Abstract:

A device, method and computer program to receive and identify incoming cell data transmitted to a cluster adapter as a request for acknowledgment from a fabric manager server so that the fabric manager server may configure a computer network. This device, method and computer allows for devices in the network to have many ports simultaneously connected to the network and still be able to receive the same request for acknowledgment on all ports without the request for acknowledgment being overwritten by other requests coming in on different ports on the same device. This is accomplished by using a fabric manager packet alias reception circuit embedded in each port to substitute the destination work queue field having a value of zero for the contents of a fabric management packet alias register located in each port. The device then responds to the request for acknowledgment and a fabric management packet alias transmission circuit then replaces the source work queue field with the value zero so that the fabric manager server will recognize the response as an acknowledgment of the devices presence.

US Patent:

6745353, Jun 1, 2004

Filed:

Mar 15, 2001

Appl. No.:

09/809443

Inventors:

Dean S. Susnow - Portland OR
Timothy Barilovits - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H02H 305

US Classification:

714706, 714 56

Abstract:

Method and apparatus for link physical error tracking that includes a one or more shift registers, one or more counters, and a comparator. The shift register receives one or more status bits for an input data stream denoting whether bytes of the input data stream have a link physical error. The counter increments an error count when receiving at least one status bit that denotes a link physical error, and decrements the error count when receiving at least one status bit from an output of the shift register that denotes a link physical error. The comparator compares the error count with a maximum value. A retrain signal is generated if the error count becomes larger than or equal to the maximum value. The retrain signal may be used to signal that a connection between two nodes needs to be retrained to get the two nodes back into synchronization. Link physical errors that occur aligned and misaligned with a rising edge of a symbol clock are trackable.

US Patent:

6747997, Jun 8, 2004

Filed:

Jun 13, 2000

Appl. No.:

09/592672

Inventors:

Dean S. Susnow - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04J 306

US Classification:

370509, 370503, 370506, 713500, 375372

Abstract:

A network interface controller connects a processing system to receive data from a network fabric through a serial link. The data on the link is clocked in a link clock domain that is different than the core clock domain of the network interface controller. A physical interface operates in the link clock domain. It has a pipeline architecture partitioned into an input register block, a decoder block and a link synchronization manager. The input register block receives the link clock and the data on the link, and transfers the data into the link clock domain. The decoder block has dual cascaded 8B/10B decoders receiving and decoding the data transferred by the input register block. The link synchronization manager manages the synchronization of the serial link according to the decoded data. An elastic buffer is connected to the output of the link synchronization manager. It is configured to output the decoded data in the core clock domain.

US Patent:

6751235, Jun 15, 2004

Filed:

Jun 27, 2000

Appl. No.:

09/604244

Inventors:

Dean S. Susnow - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04J 306

US Classification:

370503, 370388, 370510

Abstract:

A communication link is synchronized by a network interface having a transmitter in a core clock domain different from the link clock domain of the communication link. A link synchronization state machine controls the link synchronization process. The functionality of the link synchronization state machine is partitioned so that some of the functions of the link synchronization process are performed by the transmitter in the core clock domain.