David Meltzer

US Patent:

6665790, Dec 16, 2003

Filed:

Feb 29, 2000

Appl. No.:

09/514497

Inventors:

Erdem Hokenek - Yorktown Heights NY
David Meltzer - Wappingers Falls NY
Mayan Moudgill - Ossining NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1580

US Classification:

712 4, 712 7, 712 22

Abstract:

A system and method for processing operations that use data vectors each comprising a plurality of data elements, in accordance with the present invention, includes a vector data file comprising a plurality of storage elements for storing data elements of the data vectors. A pointer array is coupled by a bus to the vector data file. The pointer array includes a plurality of entries wherein each entry identifies at least one storage element in the vector data file. The at least one storage element stores at least one data element of the data vectors, wherein for at least one particular entry in the pointer array, the at least one storage element identified by the particular entry has an arbitrary starting address in the vector data file.

US Patent:

6990509, Jan 24, 2006

Filed:

Mar 8, 2002

Appl. No.:

10/093973

Inventors:

Erdem Hokenek - Yorktown Heights NY, US
Eko Lisuwandi - Cambridge MA, US
David Meltzer - Wappingers Falls NY, US
Mayan Moudgill - White Plains NY, US
Victor V. Zyuban - Peekskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/50

US Classification:

708707, 708706

Abstract:

An ultra low power adder with sum synchronization which provides a power reduction method in the binary carry propagate adders by using a carry skip technique. The invention eliminates glitches at the adder outputs by preventing signal transitions at the sum outputs until the corresponding carry signals have reached their final values, which is achieved by adding a synchronization circuitry to the sum calculation path.

US Patent:

7308559, Dec 11, 2007

Filed:

Jun 7, 2003

Appl. No.:

10/456793

Inventors:

Erdem Hokenek - Yorktown Heights NY, US
David Meltzer - Wappingers Falls NY, US
Mayan Moudgill - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/80

US Classification:

712 23, 712 22

Abstract:

A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD stage in the cascade. Each SIMD stage contains its own resources for storing operands and intermediate results (e. g. , its own register file), as well as for decoding the operations that may be executed in that stage. Within each stage, hardware resources are organized to operate in SIMD manner, so that independent SIMD operations can be executed simultaneously, one in each stage of the cascade. Intermediate operands and results flowing through the cascade are stored at the register files of the stages, and may be accessed from those register files. Data may also be brought from memory directly into the register files of the stages in the cascade.

US Patent:

7467288, Dec 16, 2008

Filed:

Nov 15, 2003

Appl. No.:

10/713502

Inventors:

Erdem Hokenek - Yorktown Heights NY, US
David Meltzer - Wappingers Falls NY, US
Mayan Moudgill - Ossining NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/76
G06F 15/82
G06F 15/80

US Classification:

712 5, 712 7, 712 22

Abstract:

A system and method for processing operations that use data vectors each comprising a plurality of data elements, in accordance with the present invention, includes a vector data file comprising a plurality of storage elements for storing data elements of the data vectors. A pointer array is coupled by a bus to the vector data file. The pointer array includes a plurality of entries wherein each entry identifies at least one storage element in the vector data file. The at least one storage element stores at least one data element of the data vectors, wherein for at least one particular entry in the pointer array, the at least one storage element identified by the particular entry has an arbitrary starting address in the vector data file.

US Patent:

20030188241, Oct 2, 2003

Filed:

Mar 29, 2002

Appl. No.:

10/112827

Inventors:

Victor Zyuban - Peekskill NY, US
Stephen Kosonocky - Wilton CT, US
David Meltzer - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R031/28

US Classification:

714/726000

Abstract:

A low-power integrated circuit containing a set of scan latches for passing data from flip-flops to test circuitry is modified such that the scan latches are formed from low-leakage transistors connected directly to the power supply so that they remain on during power-down and such that there is a data return path from the scan latches back to the flip-flops, so that the scan latches receive data from the flip-flops before a power-down mode, retain the data during power-down and return the data after power-down, thus saving on circuit area by using the scan latches for a second function. Further area is saved by using the scan trigger input to the flip-flops also for the data return path.

US Patent:

20030226077, Dec 4, 2003

Filed:

May 28, 2002

Appl. No.:

10/156900

Inventors:

Victor Zyuban - Peekskill NY, US
David Meltzer - Wappingers Falls NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G01R031/28

US Classification:

714/726000

Abstract:

A latch suitable for an integrated circuit having a test mechanism that involves scanning a set of logic circuits has a two-stage main latch and a level-sensitive scan latch, the combination operating normally as a single-phase latch and as a master-slave latch during scan mode. The scan mechanism is introduced at the second stage of the main latch, with the result that the capacitance introduced by the scan connection switches at most once per clock cycle, reducing the power load of the circuit; and the scan latch output is separated from the data output of the main latch, thereby further reducing the power load.