Claudian R Nicolesco

US Patent:

20020164876, Nov 7, 2002

Filed:

Jan 18, 2002

Appl. No.:

10/054697

Inventors:

Hans Walitzki - Portland OR, US
Howard Hogle - Portland OR, US
Wing Luk - Portland OR, US
Claudian Nicolesco - Portland OR, US

International Classification:

H01L021/302
H01L021/461

US Classification:

438/692000, 438/693000

Abstract:

According to the invention, a method for preparing multicrystalline substrates as “handle wafers” for subsequent bonding to “device layer” quality materials is disclosed. In one step, starting with a suitable substrate such as multicrystalline silicon, the substrate surface is prepared for layer transfers by using a novel CMP method in which, after a suitable period of polishing at elevated pH, a surfactant and rinse material is gradually introduced into the slurry to lower pH and remove wear materials from the slurry. In another step, a filler layer of polycrystalline silicon is transferred to the face of the polished substrate to a predetermined thickness, thus filling in surface defects remaining after the initial CMP step, and a subsequent CMP polishing step is performed. By these steps, multicrystalline substrates can be prepared with surface roughness of twenty Angstroms or less, which is suitable for defect-free bonding to device-layer materials in this embodiment.

US Patent:

20020187595, Dec 12, 2002

Filed:

Oct 30, 2001

Appl. No.:

10/000838

Inventors:

Hans Walitzki - Portland OR, US
Kurt Dichmann - Banks OR, US
Thomas Magee - Lake Oswego OR, US
Claudian Nicolesco - Portland OR, US

Assignee:

Silicon Evolution, Inc. - Vancouver WA

International Classification:

H01L021/338

US Classification:

438/184000

Abstract:

A method for the production of silicon-on-insulator (SOI) wafers for controlling the device layer thickness variations and improvement of bonding quality at the interface of the wafers is disclosed. Using standard etched wafers, a unique sequence of process steps consisting of 2-step front side grinding, free-floating simultaneous double side polishing prepares wafers with low TTV and reduced edge roll off zones. The much smaller unbonded edge zone eliminates the requirements for edge grinding or etching in most cases. When the same s-step grinding/FFS-DSP sequence is applied after bonding and annealing of a Silicon-on-Insulator package, the resulting thickness variation in the device layer is usually smaller than what would be obtained from prior art processes.

US Patent:

20030060020, Mar 27, 2003

Filed:

Oct 11, 2001

Appl. No.:

09/976452

Inventors:

Hans Walitzki - Portland OR, US
Claudian Nicolesco - Portland OR, US
Thomas Magee - Lake Oswego OR, US
Howard Hogle - Portland OR, US

Assignee:

Silicon Evolution, Inc. - Vancouver WA

International Classification:

H01L021/30
H01L021/46
H01L021/302
H01L021/461

US Classification:

438/455000, 438/692000, 438/693000

Abstract:

The present invention relates to the manufacture of substrates for semiconductor device manufacturing particularly for applications that involved wafer-to-wafer bonding for SOI or MEMS structures. Although previous techniques have been applicable to single crystal wafers using bonding and annealing, the current techniques offer the unique capability of utilizing lower cost semiconductor materials, even when they contain dislocations or other growth associated stress fields; such as poly or multi-crystalline silicon and seed, or tail ends of CZ or FZ grown ingots. This invention provides a means of obtaining superior global and local flatness, along with nanoscale roughness variations across the surfaces so that cost and throughput are optimized.

US Patent:

6147357, Nov 14, 2000

Filed:

Feb 3, 1999

Appl. No.:

9/243962

Inventors:

Claudian R. Nicolesco - Portland OR

Assignee:

Wacker Siltronic Corporation - Portland OR

International Classification:

G01N 2188

US Classification:

25055946

Abstract:

An apparatus and a method are provided for inspecting the edge micro-texture of a semiconductor wafer. The apparatus includes a diffuse hemisphere having at least one access port and has a normal axis, a laser target sphere mounted within the hemisphere, and a laser source directing a laser beam to the laser target sphere and forming a laser spot on the laser target sphere. The laser beam is reflected from the laser target sphere. A wafer chuck presents a wafer edge to the reflected laser beam, with the wafer edge being tilted from the normal axis; and there is at least one camera for detecting radiation leaving the access port. The method includes directing a laser beam to a laser target sphere which is mounted within a diffuse hemisphere; the laser beam forming a laser spot on the laser target sphere is reflected from the laser target sphere to the edge of a wafer; and radiation which leaves the hemisphere through at least one access port of the hemisphere is detected with at least one camera.