Lai C Leung

US Patent:

8618854, Dec 31, 2013

Filed:

Oct 15, 2010

Appl. No.:

12/905859

Inventors:

Chiewcharn Narathong - San Diego CA, US
Lai Kan Leung - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03L 7/06

US Classification:

327159

Abstract:

A Phase-to-Digital Converter (PDC) within a Phase-Locked Loop (PLL) includes a PDC portion and a PDC decoder portion. The PDC portion receives a reference signal FR and a feedback signal FV and generates therefrom a stream of multi-bit digital values. Each multi-bit value is indicative of a time difference between an edge of FR and a corresponding edge of FV. The PDC decoder portion includes sequential logic elements that are clocked to capture the multi-bit digital values. In order to prevent metastability, the timing of when the sequential logic elements are clocked to capture the multi-bit digital values is adjusted as a function of the phase difference between FR and FV. In one specific example, if the phase difference is small then the falling edge of FR is used to clock the sequential logic elements, whereas if the phase difference is large then the rising edge of FR is used.

US Patent:

8634512, Jan 21, 2014

Filed:

Feb 8, 2011

Appl. No.:

13/023369

Inventors:

Lai Kan Leung - San Diego CA, US
Chiewcharn Narathong - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03D 3/24

US Classification:

375376, 375215, 375294, 375327, 375371, 375373, 327156

Abstract:

A two point modulation digital phase locked loop circuit is disclosed. The circuit includes a sampling clock input that is switchable between a plurality of frequencies. The circuit also includes a sigma-delta modulator in a feedback path that receives low-pass modulation data. The circuit also includes a voltage-mode digital-to-analog converter (VDAC) that receives high-pass modulation data. The circuit also includes an analog voltage controlled oscillator coupled to the feedback path and the output of the VDAC. The circuit also includes a phase-to-digital converter (PDC) coupled to the feedback path, the sampling clock and a loop filter.

US Patent:

20130229954, Sep 5, 2013

Filed:

Feb 13, 2013

Appl. No.:

13/765992

Inventors:

Lai Kan Leung - San Marcos CA, US
Soon-Seng Lau - San Diego CA, US
Shrenik Patel - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03B 28/00

US Classification:

370280

Abstract:

A dual frequency synthesizer architecture for a wireless device operating in a time division duplex (TDD) mode is disclosed. In an exemplary design, the wireless device includes first and second frequency synthesizers. The first frequency synthesizer generates a first oscillator signal used to generate a first/receive local oscillator (LO) signal at an LO frequency for the receiver. The second frequency synthesizer generates a second oscillator signal used to generate a second/transmit LO signal at the same LO frequency for the transmitter. The two frequency synthesizers generate their oscillator signals to obtain receive and transmit LO signals at the same LO frequency when the wireless device operates in the TDD mode.

US Patent:

20220311423, Sep 29, 2022

Filed:

Mar 24, 2021

Appl. No.:

17/211716

Inventors:

- San Diego CA, US
Lai Kan Leung - San Marcos CA, US
Chirag Dipak Patel - San Diego CA, US
Xinmin Yu - San Diego CA, US
Rajagopalan Rangarajan - San Diego CA, US

International Classification:

H03H 11/22

Abstract:

An example apparatus includes a polyphase transconductance-capacitor filter. The polyphase filter includes a DC bias voltage node, a plus in-phase filter unit, a minus in-phase filter unit, a plus quadrature-phase filter unit, and a minus quadrature-phase filter unit. Each filter unit respectively includes an input node, an output node, and a control node. The polyphase filter also includes a plus in-phase switch and a minus in-phase switch. The plus in-phase switch is coupled to the control node of the plus in-phase filter unit, the DC bias voltage node, and the input node of one or both of the plus quadrature-phase filter unit and the minus quadrature-phase filter unit. The minus in-phase switch is coupled to the control node of the minus in-phase filter unit, the DC bias voltage node, and the input node of one or both of the plus quadrature-phase filter unit and the minus quadrature-phase filter unit.

US Patent:

20230099161, Mar 30, 2023

Filed:

Sep 24, 2021

Appl. No.:

17/448870

Inventors:

- San Diego CA, US
Jang Joon Lee - San Diego CA, US
Rahul Kodkani - San Diego CA, US
Aleksandar Miodrag Tasic - San Diego CA, US
Chih-Fan Liao - San Diego CA, US
Lai Kan Leung - San Marcos CA, US
Chiewcharn Narathong - Laguna Niguel CA, US

International Classification:

H03F 3/19
H03F 1/56

Abstract:

An amplifier may include multiple stages, with the multiple stages arranged in a fan-out configuration. The fan-out configuration provides multiple amplified signals at multiple amplifier output nodes, which may be coupled to a shared set of downconverters. The shared downconverters may support processing of only a smaller bandwidth than the largest possible bandwidth of an input RF signal input to the amplifier. For example, the downconverters may support a bandwidth matching a smallest bandwidth of a supported RF signal. For example, when the amplifier is intended to support 5G mmWave RF signals and 5G sub-6 GHz RF signals, the downconverters may each individually support a bandwidth of carriers in the 5G sub-6 GHz RF signals but not individually support the entire bandwidth of a possible 5G mmWave RF signal.

US Patent:

20230089220, Mar 23, 2023

Filed:

Sep 22, 2021

Appl. No.:

17/448499

Inventors:

- San Diego CA, US
Kyle David Holland - San Diego CA, US
Jian Kang - San Diego CA, US
Aleksandar Miodrag Tasic - San Diego CA, US
Chih-Fan Liao - San Diego CA, US
Yingying Li - San Diego CA, US
Lai Kan Leung - San Marcos CA, US
Chiewcharn Narathong - Laguna Niguel CA, US

International Classification:

H04B 1/16

Abstract:

Embodiments of this disclosure may include a receiver with a reconfigurable processing path for different signal conditions. Such a receiver may reconfigure between a mixer-first configuration and an amplifier-first configuration. In the mixer-first configuration, an RF input signal is not passed through an LNA for amplification before processing the RF input signal for downconversion to baseband and eventual extraction of the information in the signal. In the amplifier-first configuration, an RF input signal is passed through an LNA for amplification before processing the RF input signal for downconversion to baseband and eventual extraction of the information in the signal. Reconfiguring the receiver between mixer-first and amplifier-first configurations may be performed based on detection of jammer signals and/or measurement of signal-to-noise ratio (SNR).

US Patent:

20230057499, Feb 23, 2023

Filed:

Aug 17, 2021

Appl. No.:

17/404948

Inventors:

- San Diego CA, US
Jun TAN - San Diego CA, US
Lai Kan LEUNG - San Marcos CA, US
Timothy Donald GATHMAN - San Diego CA, US
Mehmet IPEK - Dallas TX, US
Ojas CHOKSI - San Diego CA, US

International Classification:

H04B 1/18
H03F 3/19

Abstract:

A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.

US Patent:

20210067118, Mar 4, 2021

Filed:

Aug 30, 2019

Appl. No.:

16/557974

Inventors:

- San Diego CA, US
Xinmin Yu - San Diego CA, US
Lai Kan Leung - San Marcos CA, US

International Classification:

H03G 3/30
H03K 5/02
H03F 3/45
H03F 3/62
H01Q 21/00
H03F 1/02

Abstract:

An apparatus is disclosed for bidirectional variable gain amplification. In an example aspect, an apparatus comprises an antenna element of an antenna array and a wireless transceiver. The wireless transceiver comprises a transmit path coupled to the antenna element, a receive path coupled to the antenna element, and a phase shifter disposed in both the transmit path and the receive path. The phase shifter is configured to operate in an active mode and comprises a first bidirectional variable gain amplifier and a second bidirectional variable gain amplifier.