Christopher R Hinds

US Patent:

6360189, Mar 19, 2002

Filed:

Aug 31, 1998

Appl. No.:

09/144264

Inventors:

Christopher Neal Hinds - Austin TX
David Vivian Jaggar - Austin TX
David Terrence Matheny - Austin TX

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 738

US Classification:

703 2, 708501, 708523

Abstract:

A data processing apparatus and method is provided for performing a multiply-accumulate operation A+(B*C) in response to a single instruction identifying said multiply-accumulate operation. The data processing operation comprises a multiplier for multiplying values B and C to generate an unrounded multiplication result, the multiplier further being arranged to generate first data required for rounding determination, and an adder for adding the unrounded multiplication result to a value A to generate an unrounded multiply-accumulate result, the adder further being arranged to generate second data required for rounding determination. Determination logic is then provided for using the first and second data to determine one or more rounding values required to produce a final multiply-accumulate result equivalent to the execution of a separate multiply instruction incorporating rounding, followed by a separate add instruction incorporating rounding. Rounding logic is then arranged to apply the one or more rounding values to generate the final multiply-accumulate result. By this approach, dedicated multiply-accumulate logic can be provided to enable fast execution of a multiply-accumulate instruction, whilst producing a result which is compliant with the IEEE 754-1985 standard.

US Patent:

6542916, Apr 1, 2003

Filed:

Jul 28, 1999

Appl. No.:

09/362182

Inventors:

Christopher Neal Hinds - Austin TX
David Vivian Jaggar - Austin TX
David James Seal - Cambridge, GB

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 738

US Classification:

708501, 708523

Abstract:

A data processing apparatus and method is provided for applying a floating-point multiply-accumulate operation to first, second and third operands. The apparatus comprises a multiplier for multiplying the second and third operands and applying rounding to produce a rounded multiplication result, and an adder for adding the rounded multiplication result to the first operand to generate a final result and for applying rounding to generate a rounded final result. Further, control logic is provided which is responsive to a first single instruction to control the multiplier and adder to cause the rounded final result generated by the adder to be equivalent to the subtraction of the rounded multiplication result from the first operand. In preferred embodiments, the control logic is also responsive to a further single instruction to control the multiplier and adder to cause the rounded final result generated by the adder to be equivalent to the subtraction of the rounded multiplication result from the negated first operand. By this approach, multiply-accumulate logic can be arranged to provide fast execution of a first single instruction to generate a result equivalent to the subtraction of the rounded multiplication result from the first operand, or a second single instruction to generate a result equivalent to the subtraction of the rounded multiplication result from the negated first operand, whilst producing results which are compliant with the IEEE 754-1985 standard.

US Patent:

6701427, Mar 2, 2004

Filed:

Dec 22, 1999

Appl. No.:

09/468837

Inventors:

Christopher Neal Hinds - Austin TX
Arun Kumar Varadarajan Rajagopal - Madras, IN

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 1500

US Classification:

712244, 712222, 712218, 708506

Abstract:

A data processing apparatus for processing floating point instructions is responsive to a floating point instruction to apply a floating point operation to a number of operands to produce a final result, result data being generated during a predetermined pipelined stage with further processing then being performed on the result data in one or more subsequent pipelined stages to generate the final result. Exception determination logic determines whether an exception may occur during application of the floating point operation to the operands, and to prevent the execution unit applying the floating point operation to those operands if it is determined that an exception may occur. The exception determination logic is arranged to use at least some of the predetermined control data to compensate for differences between the forwarded result data and the final result relevant when determining whether an exception may occur when processing the second floating point instruction.

US Patent:

6842849, Jan 11, 2005

Filed:

May 21, 2001

Appl. No.:

09/860777

Inventors:

Christopher Neal Hinds - Austin TX, US
Morgan Lee Reece - Pflugerville TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 938

US Classification:

712217

Abstract:

The present invention provides a system and method for locking source registers in a data processing apparatus. The data processing apparatus comprises a processing unit having a pipeline for executing a sequence of instructions, and a set of source registers for storing source data required by the processing unit when executing instructions in the sequence. A locking mechanism is then used to lock source registers dependent on configurable criteria, the configurable criteria being chosen to ensure that source registers still required for completing execution of an instruction in the pipeline are locked to prevent predetermined types of access by a subsequent instruction, the subsequent instruction only being able to enter the pipeline if the source registers relevant to that instruction can be accessed as required by the instruction. In accordance with the present invention, the processing unit has a first and second mode of operation. In the first mode of operation, the processing unit is arranged, upon determination of one or more exception conditions during execution of an instruction, to invoke a process external to the pipelined execution unit to enable execution of the instruction to be completed.

US Patent:

7016930, Mar 21, 2006

Filed:

Oct 25, 2002

Appl. No.:

10/280095

Inventors:

Christopher Neal Hinds - Austin TX, US
Neil Burgess - Cardiff, GB

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 7/52
G06F 7/38

US Classification:

708650, 708605

Abstract:

The present invention provides an apparatus and method for performing an operation on an operand or operands in order to generate a result, in which the operation is implemented by iterative execution of a recurrence equation. In each iteration, execution of the recurrence equation causes a predetermined number of bits of the result and a residual to be generated, the residual generated in a previous iteration being used as an input for the current iteration, and in the first iteration the residual comprising the operand. The apparatus comprises result digit logic operable for a current iteration to determine, having regard to a most significant n bits of the input residual, a next result digit, and residual generation logic operable for a current iteration to generate, having regard to the input residual and the next result digit, a next residual, the most significant n bits of the next residual being generated in non-redundant form and the remaining bits of the next residual being generated in redundant form. Result update logic is also provided which is operable for a current iteration to modify the result, having regard to the next result digit, to produce an updated result. Control logic is then provided to cause the iterations to continue until a predetermined condition is met, whereafter the result is indicated by the updated result and any residual existing after the final iteration.

US Patent:

7219214, May 15, 2007

Filed:

Jul 13, 2004

Appl. No.:

10/889318

Inventors:

Simon Andrew Ford - Cambridge, GB
Dominic Hugo Symes - Cambridge, GB
Andrew Christopher Rose - Cambridge, GB
David Raymond Lutz - Austin TX, US
Christopher Neal Hinds - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 9/00
G06F 9/44

US Classification:

712225, 712 22, 712223, 711154

Abstract:

A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements occupying different lanes of parallel processing in at least one of the registers. Access logic is provided which is responsive to a single access instruction to move a plurality of data elements between a chosen one of the lanes in specified registers and a structure within memory having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is operation to arrange the plurality of data elements as they are moved such that data elements of different components are stored in different specified registers within the chosen lane whilst in memory the data elements are stored as the structure.

US Patent:

7219215, May 15, 2007

Filed:

Jul 13, 2004

Appl. No.:

10/889367

Inventors:

Simon Andrew Ford - Cambridge, GB
Dominic Hugo Symes - Cambridge, GB
Andrew Christopher Rose - Cambridge, GB
David Raymond Lutz - Austin TX, US
Christopher Neal Hinds - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 9/40

US Classification:

712225, 712223, 712 22

Abstract:

A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements accessed in at least one of the registers. Access logic is operable in response to a single access instruction to move a plurality of data elements between specified registers and a continuous block of memory in which data elements are stored as an array of structures having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is further operable to rearrange the plurality of data elements as they are moved such that each specified register stores data elements of one component whilst in memory the data elements are stored as the array of structures.

US Patent:

7356553, Apr 8, 2008

Filed:

Mar 18, 2004

Appl. No.:

10/803164

Inventors:

David Raymond Lutz - Austin TX, US
Christopher Neal Hinds - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 7/465

US Classification:

708505

Abstract:

The present invention provides a data processing apparatus and method for performing a data processing operation on first and second floating point data elements, the first floating point data element specifying a first exponent and the second floating point data element specifying a second exponent. The data processing apparatus comprises processing logic providing multiple processing paths which are selectable to perform the data processing operation, including a first processing path operable to perform the data processing operation if a predetermined alignment condition exists. Further, at least one detector logic unit is provided which is operable to receive both the first exponent and the second exponent and to detect the presence of the predetermined alignment condition. Each detector logic unit comprises half adder logic operable to perform a half adder operation to logically subtract one of the first and second exponents from the other of the first and second exponents to produce at least a sum data value of sum and carry data values representing the result of the half adder operation. Further, each detector logic unit comprises generation logic operable to receive the sum data value and to generate a select signal which is set if the sum data value has a predetermined value indicating the existence of the predetermined alignment condition.