Intel Corporation - Santa Clara, CA since Jun 2008
Component Design Enginner
Texas A&M University Aug 2006 - May 2008
Graduate Assistant
Intel Corporation Sep 2007 - Dec 2007
Analog Design Intern
Atrenta Jul 2004 - Jul 2006
Sr. Software Engineer
Education:
Texas A&M University 2006 - 2008
M.S., Electrical & Computer Engineering
Netaji Subhas Institute of Technology 2000 - 2004
B.E., Instrumentation & Control
Delhi Public School - Vasant Kunj
Skills:
Verilog Static Timing Analysis Perl C Formal Verification Unix Compilers Windows Reliability Virtuoso Silicon Spyglass EDA Information Extraction TCL VLSI RTL design ASIC Computer Architecture SoC
Youtube
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